STABLE builds from yesterday.
Mike
? sys/arch/arm/patch.txt
Index: sys/arch/arm/iomd/iomd_clock.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/iomd/iomd_clock.c,v
retrieving revision 1.29
diff -u -r1.29 iomd_clock.c
--- sys/arch/arm/iomd/iomd_clock.c 18 May 2012 21:09:50 -0000 1.29
+++ sys/arch/arm/iomd/iomd_clock.c 24 Mar 2019 22:22:25 -0000
@@ -73,6 +73,12 @@
#define TIMER_FREQUENCY 2000000 /* 2MHz clock */
#define TICKS_PER_MICROSECOND (TIMER_FREQUENCY / 1000000)
+/* Macros for direct register access. Would be nice to avoid these but
+ * delay needs to use the timer device BEFORE the iomd clock device is
+ * attached as a spin based delay causes crashes at startup!
+ */
+#define IOMD_READ(a) *(volatile uint8_t *)(IOMD_ADDRESS(a))
+#define IOMD_WRITE(a,x) *(volatile uint8_t *)(IOMD_ADDRESS(a)) = (x)
static void *clockirq;
static void *statclockirq;
static struct clock_softc *clock_sc;
@@ -251,6 +257,23 @@
}
#endif
+
+static void
+initclock(void)
+{
+ timer0_count = TIMER_FREQUENCY / hz;
+
+ /* Use direct register access here rather than busspace as this
+ * function can be called BEFORE cpu_initclocks when early kerel
+ * code wants to call delay */
+ IOMD_WRITE(IOMD_T0LOW, (timer0_count >> 0) & 0xff);
+ IOMD_WRITE(IOMD_T0HIGH, (timer0_count >>8) & 0xff);
+
+ /* reload the counter */
+
+ IOMD_WRITE( IOMD_T0GO, 0);
+}
+
/*
* void cpu_initclocks(void)
*
@@ -269,18 +292,8 @@
*/
aprint_normal("clock: hz=%d stathz = %d profhz = %d\n", hz, stathz, profhz);
-
- timer0_count = TIMER_FREQUENCY / hz;
-
- bus_space_write_1(clock_sc->sc_iot, clock_sc->sc_ioh,
- IOMD_T0LOW, (timer0_count >> 0) & 0xff);
- bus_space_write_1(clock_sc->sc_iot, clock_sc->sc_ioh,
- IOMD_T0HIGH, (timer0_count >>8) & 0xff);
-
- /* reload the counter */
-
- bus_space_write_1(clock_sc->sc_iot, clock_sc->sc_ioh,
- IOMD_T0GO, 0);
+ if (!timer0_count)
+ initclock();
clockirq = intr_claim(IRQ_TIMER0, IPL_CLOCK, "tmr0 hard clk",
clockhandler, 0);
@@ -355,16 +368,47 @@
void
delay(u_int n)
{
- volatile u_int n2;
- volatile u_int i;
-
- if (n == 0) return;
- n2 = n;
- while (n2-- > 0) {
- if (cputype == CPU_ID_SA110) /* XXX - Seriously gross hack */
- for (i = delaycount; --i;);
+ u_int last;
+ u_int cur;
+ u_int acc = 0;
+ u_int oldirqstate;
+ /* Init timer if it is not already setup. */
+ if (!timer0_count)
+ initclock();
+ /* Adjust the delay count to a tick count */
+ n *= TICKS_PER_MICROSECOND;
+
+ /* Read an initial value from the timer */
+ oldirqstate = disable_interrupts(I32_bit);
+ /* Use direct access in this routine as it can be called BEFORE
+ * the clock device is attached and the bus space access becomes
+ * available! */
+ IOMD_WRITE(IOMD_T0LATCH, 0);
+
+ last = IOMD_READ(IOMD_T0LOW);
+ last += (IOMD_READ(IOMD_T0HIGH) <<8);
+ restore_interrupts(oldirqstate);
+ /* IOMD timer is countdown. So normally last > cur &
+ * last - cur is our delta. If the timer wraps while we
+ * are polling result will be cur <= last in this case we
+ * need timer0_count - cur + last for the interval as the interval
+ * is from last down to 0 and then from timer0_count down to cur.
+ */
+ while (acc <n) {
+ oldirqstate = disable_interrupts(I32_bit);
+ IOMD_WRITE(IOMD_T0LATCH, 0);
+
+ cur = IOMD_READ(IOMD_T0LOW);
+ cur += (IOMD_READ(IOMD_T0HIGH) <<8);
+
+ restore_interrupts(oldirqstate);
+
+ if (cur > last)
+ acc += timer0_count - cur + last;
else
- for (i = 8; --i;);
+ acc += last - cur;
+ /* Update our last time */
+ last = cur;
}
}
Index: sys/arch/arm/iomd/iomd_irq.S
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/iomd/iomd_irq.S,v
retrieving revision 1.16
diff -u -r1.16 iomd_irq.S
--- sys/arch/arm/iomd/iomd_irq.S 2 Dec 2013 18:36:10 -0000 1.16
+++ sys/arch/arm/iomd/iomd_irq.S 24 Mar 2019 22:22:25 -0000
@@ -412,7 +412,7 @@
#ifdef IRQSTATS
/* These symbols are used by vmstat */
- .section .rodata
+ .section .data
.global _C_LABEL(_intrnames)
_C_LABEL(_intrnames):
Index: sys/arch/arm/iomd/iomd_irqhandler.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/iomd/iomd_irqhandler.c,v
retrieving revision 1.22
diff -u -r1.22 iomd_irqhandler.c
--- sys/arch/arm/iomd/iomd_irqhandler.c 25 Oct 2014 10:58:12 -0000 1.22
+++ sys/arch/arm/iomd/iomd_irqhandler.c 24 Mar 2019 22:22:25 -0000
@@ -180,7 +180,9 @@
/* Get the interrupt name from the head of the list */
char *iptr = _intrnames + (irq * 14);
if (handler->ih_name) {
- strlcpy(iptr, handler->ih_name, 14);
+ /* kvm code expects these to be padded to the
+ * field length (13 chars + \0 in our case) */
+ snprintf(iptr, 14, "%-13.13s", handler->ih_name );
} else {
snprintf(iptr, 14, "irq %2d ", irq);
}
@@ -290,7 +292,9 @@
/* Get the interrupt name from the head of the list */
char *iptr = _intrnames + (irq * 14);
if (irqhandlers[irq] && irqhandlers[irq]->ih_name) {
- strlcpy(iptr, irqhandlers[irq]->ih_name, 14);
+ /* kvm code expects these to be padded to the
+ * field length (13 chars + \0 in our case) */
+ snprintf(iptr, 14, "%-13.13s", handler->ih_name );
} else {
snprintf(iptr, 14, "irq %2d ", irq);
}