Le dim. 31 oct. 2021 à 06:26, Michael <macallan%netbsd.org@localhost> a écrit : > If the core can do per-channel multiplication, or SIMD multiplication, > you can. The nice thing about a soft-core is that it can do whatever you need it to do :-) (and for VexRiscv, that would be umulx8/smulx8 from P[acked SIMD] I guess: <https://github.com/rdolbeau/VexRiscvBPluginGenerator/blob/master/data_Zp64.txt>, presumably followed by some re-normalizing with a packed 8-bit shift; or just a customized instruction doing both at once). > Qemu went with emulating a tgx / S24 (...) > SX has instructions to read a 32bit word into four registers Is there some sort of documentation for those? I went with the cg6 because it's supported by everything, and it had some documentation available. But I don't seem to have details on either the SX or the TCX/S24 in my archives, only the higher-level stuff (XIL for SX, stuff like that) Cordially, -- Romain Dolbeau