CVS commit: src/sys/arch/mips/ingenic

Module Name:    src
Committed By:   macallan
Date:           Tue Apr 21 06:12:41 UTC 2015

Modified Files:
        src/sys/arch/mips/ingenic: jziic.c

Log Message:
support interrupt-driven transfers


To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/mips/ingenic/jziic.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.