vivado

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

fpga dsp vhdl verilog fast-fourier-transform xilinx fft vivado altera cooley-tukey-fft digital-signal-processing fast-convolutions radix-2 integer-arithmetic route-optimization

Updated Apr 25, 2019
VHDL

HWAC-DL / hwac_object_tracker

Star

FPGA accelerated TinyYOLO v2 object detection neural network

fpga detection verilog xilinx vivado pynq tinyyolo

Updated Jul 31, 2018
HTML

li3tuo4 / rc-fpga-zcu

Star

Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)

rocket-chip vivado risc-v linux-boot fpga-board zcu102 zynqmp

Updated Jan 30, 2020
Tcl

tongplw / HW-Syn-Lab

Star

⚙Hardware Synthesis Laboratory Using Verilog

hardware verilog xilinx vivado uart vga basys3 hardware-synthesis

Updated May 10, 2020
Verilog

tymonx / virtio

Star

Virtio implementation in SystemVerilog

cmake fpga model rtl verilog xilinx vivado systemverilog systemc hdl virtio verilator quartus

Updated Jan 23, 2018
SystemVerilog

nextbytes / ARM-LEGv8

Star

Verilog Implementation of an ARM LEGv8 CPU

arm verilog xilinx isa vivado hazard-detection ldr pipeline-cpu single-cycle hennessy patterson legv8-arm multi-cycle arm-legv8-simulator forwarding-unit

Updated Oct 3, 2018
Verilog

Domipheus / ArtyS7-RPU-SoC

Star

Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.

c fpga firmware vhdl riscv spi vivado apache2 hdmi fpga-soc risc-v xilinx-vivado dvid riscv32

Updated May 28, 2020
VHDL

pothosware / PothosZynq

Star

DMA source and sink blocks for Xilinx Zynq FPGAs

fpga zynq xilinx vivado dma pothos pothos-framework

Updated May 19, 2020
VHDL

Goshik92 / SHA256Hasher

Star

SHA-256 IP core for ZedBoard (Zynq SoC)

arm fpga zynq xilinx sha256 vivado systemverilog soc zedboard

Updated Jun 22, 2018
Verilog

Elphel / vdt-plugin

Star

mirror of https://git.elphel.com/Elphel/vdt-plugin

eclipse ide eclipse-plugin verilog vivado icarus-verilog gtkwave quartus cocotb

Updated Nov 29, 2017
Java

SymbiFlow / prjuray

Star

Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

fpga xilinx vivado fuzzer xilinx-fpga bitstream ultrascale symbiflow ultrascale-plus

Updated Jul 21, 2020
SystemVerilog

FloyedShen / mnist_hls

Star

Lenet for MNIST handwritten digit recognition using Vivado hls tool

zynq hls vivado zedboard fpga-accelerator vivado-hls mnist-hls

Updated Jul 22, 2020
Objective-C

fkd151136 / mips-cpu

Star

verilog vivado

Updated Dec 2, 2017
VHDL

lite-david / comet

Star

RISC-V ISA based 32-bit processor written in HLS

asic fpga hls comet isa vivado risc catapult

Updated Nov 7, 2019
C

rodrigomelo9 / verifying-foss-hdl-synthesizers

Star

a project to check the FOSS synthesizers against vendors EDA tools

vivado ise ghdl yosys iverilog verilator quartus pyfpga ghdl-yosys-plugin foss-synthesizers

Updated May 18, 2020
Makefile

b1f6c1c4 / Deep-DarkFantasy

Star

Global Dark Mode for ALL apps on ANY platforms.

fpga zynq dark-theme verilog xilinx vivado verilog-hdl dark-mode zynq-7000 dark-mode-toggle

Updated Jul 21, 2020
Verilog

suoglu / Fixed-Floating-Point-Adder-Multiplier

Star

16-bit Adder Multiplier hardware on Digilent Basys 3

fpga hardware verilog vivado fixed-point floating-point adder multiplier

Updated Aug 1, 2020
Verilog

eugene-tarassov / vivado-risc-v

Star

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

linux fpga xilinx vivado risc-v nexys-video

Updated Aug 9, 2020
Java

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