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The Wayback Machine - http://web.archive.org/web/20200825093352/https://github.com/topics/openrisc
Here are
25 public repositories
matching this topic...
Online OR1K Emulator running Linux
Updated
Aug 18, 2020
JavaScript
All CPU and MCU documentation in one place
mor1kx - an OpenRISC 1000 processor IP core
Updated
Aug 1, 2020
Verilog
Generating the call graph from elf binary file
Updated
Jun 23, 2020
Assembly
An OpenRISC 1000 Multicore Virtual Platform
An OpenRISC 1000 Instruction Set Simulator
Updated
Aug 5, 2020
SystemVerilog
System on Chip verified with UVM
Updated
Aug 25, 2020
SystemVerilog
Lisp-based stackless interpreter and platform, including microthreading. Features taken from Lisp and Erlang.
Processing Unit with OpenRISC-32 / OpenRISC-64
Updated
Aug 25, 2020
SystemVerilog
Processing Unit verified with UVM
Updated
Aug 25, 2020
SystemVerilog
System on Chip with OpenRISC-32 / OpenRISC-64
Updated
Aug 25, 2020
SystemVerilog
MPSoC with OpenRISC-32 / OpenRISC-64
Updated
Dec 23, 2016
Assembly
OpenCpuX wrapper for the or1kiss OpenRISC ISS
Examples of Applications for Nanvix
Updated
Aug 24, 2020
Makefile
Baremetal Libraries for Nanvix
FPU verification tool for OpenRISC based on softfloat library
OpenRISC processor IP core based on Tomasulo algorithm
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The NoC primitives are missing cocotb tests. Old code by @wallento is available at imphil/optimsoc@32162b1 and can potentially be used as starting point.