Developer-Y / cs-video-courses

List of Computer Science courses with video lectures.

programming-language computer-science security machine-learning bioinformatics web-development computer-vision algorithms robotics computer-graphics databases stanford-university embedded-systems systems quantum-computing computer-architecture computer-scientists database-systems harvard-university iit-delhi state-university

Updated Jul 15, 2020

MattPD / cpplinks

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A categorized list of C++ resources.

debugging c-plus-plus cplusplus cpp assembly compilers computer-architecture

Updated Aug 28, 2020

jsdf / little-virtual-computer

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Learn how computers work by simulating them in Javascript

emulation computer-architecture

Updated Apr 5, 2019
JavaScript

mortbopet / Ripes

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A graphical processor simulator and assembly editor for the RISC-V ISA

education processor-architecture qt simulator computer-architecture risc risc-v cpu-emulator

Updated Aug 28, 2020
C++

MIPT-ILab / mipt-mips

Star

Open

Verify correctness of read-after-write behavior

pavelkryukov commented Mar 18, 2020

Some RISC-V instructions perform writes to 2 destinations, either 2 register or register or program counter. In cases if the source of one sub-operation matches a destination of another one, the order of result output is important. The examples are jalr and instruction operating with CSRs:

riscv/riscv-tests#258
riscv/riscv-tests#263

Your obj

Fix incompleted RISC-V B instructions

Open

Implement remaining RISC-V B instructions

Find more good first issues →

baquer / GATE-and-CSE-Resources-for-Students

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📚 📖 📚CSE GATE Resources for GATE and CSE Aspirants 😎 😁 . Show your ❤️ by ⭐️⭐️

algorithm datastructures cse operating-system database-management computer-architecture gate compiler-design digital-design c-programming computer-network automata-theory

Updated Apr 13, 2020

umd-memsys / DRAMSim2

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DRAMSim2: A cycle accurate DRAM simulator

c-plus-plus simulator dram computer-architecture

Updated Oct 2, 2018
C++

jobhope / TechnicalNote

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Repository to store what we have studied. 📖 We want everyone to get a job through TechnicalNote.

github javascript java windows programming-language security algorithm database web cpp network linear-algebra sort operating-system data-structures software-engineering computer-architecture technical-notes tech-interview

Updated Aug 19, 2020

err0r500 / foundational-knowledge-for-programmers

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List of resources about foundational knowledge for programmers (supposed to last a few decades)

computer-science awesome cryptography networking algorithms linear-algebra type-theory category-theory programming-languages programming-paradigms awesome-list computer-architecture software-architecture algorithms-and-data-structures proof-theory

Updated Apr 7, 2020

JackonYang / paper-reading

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深度学习论文阅读、数据仓库实践体验。比做算法的懂工程落地，比做工程的懂算法模型。

nlp deprecated arxiv computer-architecture distribute computer-vi data-ware

Updated Apr 14, 2020
Jupyter Notebook

hao-lh / books-making-you-better

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A list of classic books make better you understand not only how it works, but why it works.

machine-learning reinforcement-learning computer-vision deep-learning linear-algebra statistical-learning inference stanford-university high-performance-computing bayesian-inference computer-architecture probabilistic-graphical-models hao 5th robert-tibshirani

Updated Aug 15, 2020

coderick14 / ARMed

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A terminal-based emulator of the ARM instruction set written in Golang

emulator golang arm assembly computer-architecture computer-organization

Updated Jan 16, 2018
Go

rajesh-s / computer-engineering-resources

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A curated list of Computer Engineering resources

computer-engineering computer-architecture

Updated Aug 17, 2020

mhyousefi / MIPS-pipeline-processor

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A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

pipeline verilog computer-architecture hazard-detection mips-processor forwarding-unit

Updated Aug 24, 2019
Verilog

vmmc2 / Vulcan

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RISC-V Instruction Set Simulator (Built for education).

education simulator assembly computer-architecture risc risc-v

Updated Aug 28, 2020
Dart

Maecenas / ICS-15213-CSAPP3e-CMU

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🎓🐳 Lab Assignments and Developing Environments of the Introduction to Computer Systems, 15-213 CMU

computer-science architecture csapp ics computer-architecture cmu

Updated Nov 17, 2019
C

skyzh / RISCV-Simulator

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💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.

cmake cpu pipeline cpp riscv gtest computer-architecture speculation branch-prediction riscv32 riscv-simulator riscv-emulator tomasulo-algorithm

Updated Jul 2, 2020
C++

Mariotti94 / WebRISC-V

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WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]

php education processor-architecture simulator pipeline assembly computer-architecture risc risc-v pipeline-simulation-environment

Updated Jul 5, 2020
PHP

harvard-edge / MAVBench

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Simulator + benchmark suite for Micro Aerial Vehicle design.

benchmark simulator hardware sensor flight-controller drones computer-architecture actuators system-design airsim autonomous-machines

Updated Jul 19, 2020
Python

meton-robean / ResearchNote

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通过issue和README来记录日常学习研究笔记关注机器学习系统，深度学习， LLVM，性能剖视， Linux操作系统内核话题关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using github issue and markdown! (inculding Machine Learning algs and system, LLVM, Linux kernel, java, python, c++, golang)

python java golang notes llvm linux-kernel computer blogs computer-architecture

Updated May 24, 2020

jlperona-teaching / ecs154a-winter20

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Course files for ECS 154A in Winter Quarter 2020.

education computer-architecture ucdavis

Updated Mar 13, 2020
Python

guptaanmol184 / nand2tetris

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Nand2tetris course

processor assembly nand2tetris computer-architecture nand2tetris-assignments

Updated May 16, 2017
Assembly

yuri-pechatnov / caos_2019-2020

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Материалы для студентов ФПМИ

education computer-architecture low-level-programming seminars

Updated Jun 26, 2020
Jupyter Notebook

ILLIXR / ILLIXR

Star

Open

Replace `std::mutex` with `std::shared_mutex`, where relevant (allow reader-concurrency).

charmoniumQ opened Aug 21, 2020

feature good first issue

Open

Standardize clock in every component

Open

Stylistic improvements

Find more good first issues →

rafi007akhtar / CSE-resources

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A collection of curated resources for learning Computer Science subjects and skills, that I garnered throughout my tenure as a CSE student. Contributions, and report of broken links are welcome.

github android git machine-learning algorithm web-development networking deep-learning dbms discrete-mathematics software-engineering operating-systems computer-architecture computer-organization automata-theory

Updated Mar 21, 2019

chenxuhao / gardenia

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GARDENIA: Graph Analytics Repository for Designing Efficient Next-generation Accelerators

benchmarking graph-algorithms opencl openmp parallel-computing cuda gpu-computing heterogeneous-parallel-programming computer-architecture sparse-matrix benchmark-suite xeon-phi accelerators

Updated Jul 29, 2020
Cuda

miglopst / PIM_NDP_papers

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ram arch pim circuit computer-architecture ndp memory-systems process-in-memory near-data-processing survey-papers

Updated Jan 9, 2019

skyzh / mips-simulator

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💻 A 5-stage pipeline MIPS CPU design in Haskell.

haskell cpu mips computer-architecture mips-emulator mips-simulator

Updated Jul 2, 2020
Haskell

zslwyuan / PAAS_V1.0

Star

PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems

fpga simulation vhdl verilog computer-architecture gem5 co-simulation cpu-fpga

Updated Apr 13, 2020
Ada

neelkshah / MIPS-Processor

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5-stage pipelined 32-bit MIPS microprocessor in Verilog

verilog microprocessor stage computer-architecture microprocessors verilog-hdl mips-architecture mips-processor bits-pilani computer-organization verilog-components verilog-snippets mips-instructions computer-organisation verilog-programs verilog-simulator verilog-project

Updated Apr 3, 2020
Verilog

computer-architecture

Here are 452 public repositories matching this topic...

Developer-Y / cs-video-courses

MattPD / cpplinks

jsdf / little-virtual-computer

mortbopet / Ripes

MIPT-ILab / mipt-mips

Verify correctness of read-after-write behavior

Fix incompleted RISC-V B instructions

Implement remaining RISC-V B instructions

baquer / GATE-and-CSE-Resources-for-Students

umd-memsys / DRAMSim2

jobhope / TechnicalNote

err0r500 / foundational-knowledge-for-programmers

JackonYang / paper-reading

hao-lh / books-making-you-better

coderick14 / ARMed

rajesh-s / computer-engineering-resources

mhyousefi / MIPS-pipeline-processor

vmmc2 / Vulcan

Maecenas / ICS-15213-CSAPP3e-CMU

skyzh / RISCV-Simulator

Mariotti94 / WebRISC-V

harvard-edge / MAVBench

meton-robean / ResearchNote

jlperona-teaching / ecs154a-winter20

guptaanmol184 / nand2tetris

yuri-pechatnov / caos_2019-2020

ILLIXR / ILLIXR

Replace `std::mutex` with `std::shared_mutex`, where relevant (allow reader-concurrency).

Standardize clock in every component

Stylistic improvements

rafi007akhtar / CSE-resources

chenxuhao / gardenia

miglopst / PIM_NDP_papers

skyzh / mips-simulator

zslwyuan / PAAS_V1.0

neelkshah / MIPS-Processor

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