mips
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Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Sparc, SystemZ, TMS320C64x, Web Assembly, X86, X86_64, XCore) + bindings.
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Oct 28, 2020 - C
Plasma is an interactive disassembler for x86/ARM/MIPS. It can generates indented pseudo-code with colored syntax.
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May 16, 2020 - Python
Binary Analysis Platform
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Oct 26, 2020 - OCaml
The OpenSource Disassembler
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Oct 27, 2020 - C++
Simple C compiler
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Oct 6, 2020 - C
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
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Jul 7, 2020 - SystemVerilog
C--compiler which implements LL(1)\LR(0)\SLR\LR(1) and semantic analysis and MIPS generate
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Nov 30, 2019 - Python
Simple and lightweight source-based multi-platform Linux distribution with musl libc.
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Oct 25, 2020 - C
Cross complie shadowsocks for UBNT devices based on mipsel or mips64
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Mar 22, 2020 - Shell
A curated list of Nintendo 64 development resources including toolchains, documentation, emulators, and more
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Oct 27, 2020 - Python
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Some RISC-V instructions perform writes to 2 destinations, either 2 register or register or program counter. In cases if the source of one sub-operation matches a destination of another one, the order of result output is important. The examples are
jalrand instruction operating with CSRs:riscv/riscv-tests#258
riscv/riscv-tests#263
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