List of Computer Science courses with video lectures.

A categorized list of C++ resources.

Learn how computers work by simulating them in Javascript

A graphical processor simulator and assembly editor for the RISC-V ISA

📚 📖 📚CSE GATE Resources for GATE and CSE Aspirants 😎 😁 . Show your ❤️ by ⭐️⭐️

Repository to store what we have studied. 📖 We want everyone to get a job through TechnicalNote.

DRAMSim2: A cycle accurate DRAM simulator

List of resources about foundational knowledge for programmers (supposed to last a few decades)

深度学习论文阅读、数据仓库实践体验。比做算法的懂工程落地，比做工程的懂算法模型。

RISC-V Instruction Set Simulator (Built for education).

A list of classic books make better you understand not only how it works, but why it works.

A curated list of Computer Engineering resources

A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

🎓🐳 Lab Assignments and Developing Environments of the Introduction to Computer Systems, 15-213 CMU

💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.

A terminal-based emulator of the ARM instruction set written in Golang

WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]

Using HDL, from Boolean algebra and elementary logic gates to building a Central Processing Unit, a memory system, and a hardware platform, leading up to a 16-bit general-purpose computer. Then, implementing the modern software hierarchy designed to enable the translation and execution of object-based, high-level languages on a bare-bone computer hardware platform; Including Virtual machine,Compiler and Operating system.

通过issue和README来记录日常学习研究笔记 关注 机器学习系统，深度学习， LLVM，性能剖视， Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using github issue and markdown! (inculding Machine Learning algs and system, LLVM, Linux kernel, java, python, c++, golang)

Simulator + benchmark suite for Micro Aerial Vehicle design.

Материалы для студентов ФПМИ

Nand2tetris course

Course files for ECS 154A in Winter Quarter 2020.

A collection of curated resources for learning Computer Science subjects and skills, that I garnered throughout my tenure as a CSE student. Contributions, and report of broken links are welcome.

💻 A 5-stage pipeline MIPS CPU design in Haskell.

This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum

5-stage pipelined 32-bit MIPS microprocessor in Verilog