lowRISC / opentitan
OpenTitan: Open source silicon root of trust
| Nov | DEC | Jan |
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OpenTitan: Open source silicon root of trust
open-source Ethenet media access controller for Ariane on Genesys-2
RISC-V Debug Support for our PULP RISC-V Cores
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
[UNRELEASED] FP div/sqrt unit for transprecision
IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs
AXI Adapter(s) for RISC-V Atomic Operations
Common SystemVerilog components
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Simple single-port AXI memory interface
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