RISC-V

ncnn is a high-performance neural network inference framework optimized for the mobile platform

Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Sparc, SystemZ, TMS320C64x, Web Assembly, X86, X86_64, XCore) + bindings.

Rocket Chip Generator

Rust version of THU uCore OS. Linux compatible.

A FPGA friendly 32 bit RISC-V CPU implementation

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

A size-optimized, customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

RISC-V simulator for x86-64

SweRV EH1 core

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

RISC-V Assembler and Runtime Simulator

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

A self-hosting and educational C compiler

Maxine VM: A meta-circular research VM

RISC-V processor emulator written in Rust+WASM

Simple RISC-V 3-stage Pipeline in Chisel

RISC-V Supervisor Binary Interface (RISC-V SBI) implementation in Rust; runs on M-mode; good support for embedded Rust ecosystem

CKB's vm, based on open source RISC-V ISA

A compiler for ARM, X86, MSP430, xtensa and more implemented in pure Python