| Jul | AUG | Sep |
| 16 | ||
| 2020 | 2021 | 2022 |
COLLECTED BY
Collection: Wide Crawl Number 18
| Part | Package | Pin Spacing | I/Os | nextpnr opts | arachne-pnr opts | icetime opts |
|---|---|---|---|---|---|---|
| iCE40-LP1K-SWG16TR | 16-ball WLCSP (1.40 x 1.48 mm) | 0.35 mm | 10 | --lp1k --package swg16tr | -d 1k -P swg16tr | -d lp1k |
| iCE40-UP3K-UWG30 | 30-ball WLCSP (2.15 x 2.55 mm) | 0.40 mm | 21 | --up5k --package uwg30 | -d 5k -P uwg30 | -d up5k |
| iCE40-UP5K-UWG30 | 30-ball WLCSP (2.15 x 2.55 mm) | 0.40 mm | 21 | --up5k --package uwg30 | -d 5k -P uwg30 | -d up5k |
| iCE40-LP384-CM36 | 36-ball ucBGA (2.5 x 2.5 mm) | 0.40 mm | 25 | --lp384 --package cm36 | -d 384 -P cm36 | -d lp384 |
| iCE40-LP1K-CM36 | 36-ball ucBGA (2.5 x 2.5 mm) | 0.40 mm | 25 | --lp1k --package cm36 | -d 1k -P cm36 | -d lp1k |
| iCE40-LP384-CM49 | 49-ball ucBGA (3 x 3 mm) | 0.40 mm | 37 | --lp384 --package cm49 | -d 384 -P cm49 | -d lp384 |
| iCE40-LP1K-CM49 | 49-ball ucBGA (3 x 3 mm) | 0.40 mm | 35 | --lp1k --package cm49 | -d 1k -P cm49 | -d lp1k |
| iCE40-LP1K-CM81 | 81-ball ucBGA (4 x 4 mm) | 0.40 mm | 63 | --lp1k --package cm81 | -d 1k -P cm81 | -d lp1k |
| iCE40-LP4K-CM81 | 81-ball ucBGA (4 x 4 mm) | 0.40 mm | 63 | --lp8k --package cm81:4k | -d 8k -P cm81:4k | -d lp8k |
| iCE40-LP8K-CM81 | 81-ball ucBGA (4 x 4 mm) | 0.40 mm | 63 | --lp9k --package cm81 | -d 8k -P cm81 | -d lp8k |
| iCE40-LP1K-CM121 | 121-ball ucBGA (5 x 5 mm) | 0.40 mm | 95 | --lp1k --package cm121 | -d 1k -P cm121 | -d lp1k |
| iCE40-LP4K-CM121 | 121-ball ucBGA (5 x 5 mm) | 0.40 mm | 93 | --lp8k --package cm121:4k | -d 8k -P cm121:4k | -d lp8k |
| iCE40-LP8K-CM121 | 121-ball ucBGA (5 x 5 mm) | 0.40 mm | 93 | --lp8k --package cm121 | -d 8k -P cm121 | -d lp8k |
| iCE40-LP4K-CM225 | 225-ball ucBGA (7 x 7 mm) | 0.40 mm | 167 | --lp8k --package cm225:4k | -d 8k -P cm225:4k | -d lp8k |
| iCE40-LP8K-CM225 | 225-ball ucBGA (7 x 7 mm) | 0.40 mm | 178 | --lp8k --package cm225 | -d 8k -P cm225 | -d lp8k |
| iCE40-HX8K-CM225 | 225-ball ucBGA (7 x 7 mm) | 0.40 mm | 178 | --hx8k --package cm225 | -d 8k -P cm225 | -d hx8k |
| iCE40-LP384-QN32 | 32-pin QFN (5 x 5 mm) | 0.50 mm | 21 | --lp384 --package qn32 | -d 384 -P qn32 | -d lp384 |
| iCE40-UP5K-SG48 | 48-pin QFN (7 x 7 mm) | 0.50 mm | 39 | --up5k --package sg48 | -d 5k -P sg48 | -d up5k |
| iCE40-LP1K-QN84 | 84-pin QFNS (7 x 7 mm) | 0.50 mm | 67 | --lp1k --package qn84 | -d 1k -P qn84 | -d lp1k |
| iCE40-LP1K-CB81 | 81-ball csBGA (5 x 5 mm) | 0.50 mm | 62 | --lp1k --package cb81 | -d 1k -P cb81 | -d lp1k |
| iCE40-LP1K-CB121 | 121-ball csBGA (6 x 6 mm) | 0.50 mm | 92 | --lp1k --package cb121 | -d 1k -P cb121 | -d lp1k |
| iCE40-HX1K-CB132 | 132-ball csBGA (8 x 8 mm) | 0.50 mm | 95 | --hx1k --package cb132 | -d 1k -P cb132 | -d hx1k |
| iCE40-HX4K-CB132 | 132-ball csBGA (8 x 8 mm) | 0.50 mm | 95 | --hx8k --package cb132:4k | -d 8k -P cb132:4k | -d hx8k |
| iCE40-HX8K-CB132 | 132-ball csBGA (8 x 8 mm) | 0.50 mm | 95 | --hx8k --package cb132 | -d 8k -P cb132 | -d hx8k |
| iCE40-HX1K-VQ100 | 100-pin VQFP (14 x 14 mm) | 0.50 mm | 72 | --hx1k --package vq100 | -d 1k -P vq100 | -d hx1k |
| iCE40-HX1K-TQ144 | 144-pin TQFP (20 x 20 mm) | 0.50 mm | 96 | --hx1k --package tq144 | -d 1k -P tq144 | -d hx1k |
| iCE40-HX4K-TQ144 | 144-pin TQFP (20 x 20 mm) | 0.50 mm | 107 | --hx8k --package tq144:4k | -d 8k -P tq144:4k | -d hx8k |
| iCE40-HX4K-BG121 | 121-ball caBGA (9 x 9 mm) | 0.80 mm | 93 | --hx8k --package bg121:4k | -d 8k -P bg121:4k | -d hx8k |
| iCE40-HX8K-BG121 | 121-ball caBGA (9 x 9 mm) | 0.80 mm | 93 | --hx8k --package bg121 | -d 8k -P bg121 | -d hx8k |
| iCE40-HX8K-CT256 | 256-ball caBGA (14 x 14 mm) | 0.80 mm | 206 | --hx8k --package ct256 | -d 8k -P ct256 | -d hx8k |
yosys -p "synth_ice40 -blif rot.blif" rot.v arachne-pnr -d 1k -p rot.pcf rot.blif -o rot.asc icepack rot.asc rot.bin iceprog rot.binA simple timing analysis report can be generated using the icetime utility:
icetime -tmd hx1k rot.asc
sudo apt-get install build-essential clang bison flex libreadline-dev \
gawk tcl-dev libffi-dev git mercurial graphviz \
xdot pkg-config python python3 libftdi-dev \
qt5-default python3-dev libboost-all-dev cmake libeigen3-dev
On Fedora 24 the following command installs all prerequisites:
sudo dnf install make automake gcc gcc-c++ kernel-devel clang bison \
flex readline-devel gawk tcl-devel libffi-devel git mercurial \
graphviz python-xdot pkgconfig python python3 libftdi-devel \
qt5-devel python3-devel boost-devel boost-python3-devel eigen3-devel
Note: All tools will be installed relative to /usr/local
Installing the IceStorm Tools (icepack, icebox, iceprog, icetime, chip databases):
git clone https://github.com/YosysHQ/icestorm.git icestorm cd icestorm make -j$(nproc) sudo make installInstalling Arachne-PNR (place&route tool, predecessor to NextPNR):
git clone https://github.com/cseed/arachne-pnr.git arachne-pnr cd arachne-pnr make -j$(nproc) sudo make installInstalling NextPNR (place&route tool, Arachne-PNR replacement):
git clone https://github.com/YosysHQ/nextpnr nextpnr cd nextpnr cmake -DARCH=ice40 -DCMAKE_INSTALL_PREFIX=/usr/local . make -j$(nproc) sudo make installInstalling Yosys (Verilog synthesis):
git clone https://github.com/YosysHQ/yosys.git yosys cd yosys make -j$(nproc) sudo make installBoth place and route tools (Arachne-PNR & NextPNR) convert the IceStorm text chip databases into the respective PNR binary chip databases during build. Always rebuild the PNR tools after updating your IceStorm installation. Notes for Linux: Create a file /etc/udev/rules.d/53-lattice-ftdi.rules with the following line in it to allow uploading bit-streams to a Lattice iCEstick and/or a Lattice iCE40-HX8K Breakout Board as unprivileged user:
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6010", MODE="0660", GROUP="plugdev", TAG+="uaccess"
Notes for Archlinux: just install icestorm-git, arachne-pnr-git and yosys-git from the Arch User Repository (no need to follow the install instructions above).
Notes for OSX: Please follow the additional instructions for OSX to install on OSX.
Please file an issue on github if you have additional notes to
share regarding the install procedures on the operating system of your choice.
.logic_tile 12 12 000000000000000000000000000000000000000000000000000000 000000000000000000000011010000000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000001011000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000 000000000000000000000000001000001000010101010000000000 000000000000000000000000000101010000101010100000000000This bits are referred to as By[x] in the documentation. For example, B0 is the first line, B0[0] the first bit in the first line, and B15[53] the last bit in the last line. The icebox_explain program can be used to turn this block of config bits into a description of the cell configuration:
.logic_tile 12 12 LC_7 0101010110101010 0000 buffer local_g0_2 lutff_7/in_3 buffer local_g1_4 lutff_7/in_0 buffer sp12_h_r_18 local_g0_2 buffer sp12_h_r_20 local_g1_4IceBox contains a database of the wires and configuration bits that can be found in iCE40 tiles. This database can be accessed via the IceBox Python API. But IceBox is a large hack. So it is recommended to only use the IceBox API to export this database into a format that fits the target application. See icebox_chipdb for an example program that does that. The recommended approach for learning how to use this documentation is to synthesize very simple circuits using Yosys and Arachne-pnr, run the icestorm tool icebox_explain on the resulting bitstream files, and analyze the results using the HTML export of the database mentioned above. icebox_vlog can be used to convert the bitstream to Verilog. The output file of this tool will also outline the signal paths in comments added to the generated Verilog code. For example, consider the following Verilog and PCF files:
// example.v module top (input a, b, output y); assign y = a & b; endmodule # example.pcf set_io a 1 set_io b 10 set_io y 11And run them through Yosys, Arachne-PNR and IcePack:
$ yosys -p 'synth_ice40 -top top -blif example.blif' example.v $ arachne-pnr -d 1k -o example.asc -p example.pcf example.blif $ icepack example.asc example.binWe would get something like the following icebox_explain output:
$ icebox_explain example.asc Reading file 'example.asc'.. Fabric size (without IO tiles): 12 x 16 .io_tile 0 10 IOB_1 PINTYPE_0 IOB_1 PINTYPE_3 IOB_1 PINTYPE_4 IoCtrl IE_0 IoCtrl IE_1 IoCtrl REN_0 buffer local_g0_5 io_1/D_OUT_0 buffer logic_op_tnr_5 local_g0_5 .io_tile 0 14 IOB_1 PINTYPE_0 IoCtrl IE_1 IoCtrl REN_0 buffer io_1/D_IN_0 span4_vert_b_6 .io_tile 0 11 IOB_0 PINTYPE_0 IoCtrl IE_0 IoCtrl REN_1 routing span4_vert_t_14 span4_horz_13 .logic_tile 1 11 LC_5 0001000000000000 0000 buffer local_g0_0 lutff_5/in_1 buffer local_g3_0 lutff_5/in_0 buffer neigh_op_lft_0 local_g0_0 buffer sp4_h_r_24 local_g3_0And something like the following icebox_vlog output:
$ icebox_vlog -p example.pcf example.asc // Reading file 'example.asc'.. module chip (output y, input b, input a); wire y; // io_0_10_1 // (0, 10, 'io_1/D_OUT_0') // (0, 10, 'io_1/PAD') // (0, 10, 'local_g0_5') // (0, 10, 'logic_op_tnr_5') // (0, 11, 'logic_op_rgt_5') // (0, 12, 'logic_op_bnr_5') // (1, 10, 'neigh_op_top_5') // (1, 11, 'lutff_5/out') // (1, 12, 'neigh_op_bot_5') // (2, 10, 'neigh_op_tnl_5') // (2, 11, 'neigh_op_lft_5') // (2, 12, 'neigh_op_bnl_5') wire b; // io_0_11_0 // (0, 11, 'io_0/D_IN_0') // (0, 11, 'io_0/PAD') // (1, 10, 'neigh_op_tnl_0') // (1, 10, 'neigh_op_tnl_4') // (1, 11, 'local_g0_0') // (1, 11, 'lutff_5/in_1') // (1, 11, 'neigh_op_lft_0') // (1, 11, 'neigh_op_lft_4') // (1, 12, 'neigh_op_bnl_0') // (1, 12, 'neigh_op_bnl_4') wire a; // io_0_14_1 // (0, 11, 'span4_horz_13') // (0, 11, 'span4_vert_t_14') // (0, 12, 'span4_vert_b_14') // (0, 13, 'span4_vert_b_10') // (0, 14, 'io_1/D_IN_0') // (0, 14, 'io_1/PAD') // (0, 14, 'span4_vert_b_6') // (0, 15, 'span4_vert_b_2') // (1, 11, 'local_g3_0') // (1, 11, 'lutff_5/in_0') // (1, 11, 'sp4_h_r_24') // (1, 13, 'neigh_op_tnl_2') // (1, 13, 'neigh_op_tnl_6') // (1, 14, 'neigh_op_lft_2') // (1, 14, 'neigh_op_lft_6') // (1, 15, 'neigh_op_bnl_2') // (1, 15, 'neigh_op_bnl_6') // (2, 11, 'sp4_h_r_37') // (3, 11, 'sp4_h_l_37') assign y = /* LUT 1 11 5 */ b ? a : 0; endmodule
@MISC{IceStorm,
author = {Claire Wolf and Mathias Lasser},
title = {Project IceStorm},
howpublished = "\url{http://bygone.clairexen.net/icestorm/}"
}