verilog

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

open-source 802.11 WiFi baseband chip/FPGA design

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

GPGPU microprocessor architecture

A FPGA friendly 32 bit RISC-V CPU implementation

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Haskell to VHDL/Verilog/SystemVerilog compiler

❄️ Visual editor for open FPGA boards

A repository of gate-level simulators and tools for the original Game Boy.

HDL libraries and projects

Scala based HDL

PlatformIO IDE for VSCode: The next generation integrated development environment for IoT

A small, light weight, RISC CPU soft core

Package manager and build abstraction tool for FPGA/ASIC development

This project will compile verilog (a hardware description language) into factorio blueprints.

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

SERV - The SErial RISC-V CPU

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

PlatformIO IDE for Atom: The next generation integrated development environment for IoT

Hardware Description Languages

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

A Just-In-Time Compiler for Verilog from VMware Research

🌱 Open source ecosystem for open FPGA boards

OpenROAD's unified application implementing an RTL-to-GDS Flow