microarchitecture

Open-source high-performance RISC-V processor

A cross platform C99 library to get cpu features at runtime.

Simple yet fancy CPU architecture fetching tool

inVtero.net: A high speed (Gbps) Forensics, Memory integrity & assurance. Includes offensive & defensive memory capabilities. Find/Extract processes, hypervisors (including nested) in memory dumps using microarchitechture independent Virtual Machiene Introspection techniques

Achieve peak performance on x86 CPUs and NVIDIA GPUs

Microarchitectural exploitation and other hardware attacks.

High performance Bitcoin development platform

A small RISC-V core (SystemVerilog)

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

Performance Counter Measurements at the cycle granularity

FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64

Sequential entries of a long number with offset for the FPGA microarchitecture on system verilog

💻 Custom 64-bit pipelined RISC processor.

One Instruction Set Computer

A customizable hardware prefetching framework using online reinforcement learning as described in the MICRO 2021 paper by Bera and Kanellopoulos et al.

A small RISC-V core (VHDL)

Virtualization of a 32-bit ARM-like processor with native execution.

💻 Dual-core 16-bit RISC processor.

An implementation of the LC-3 architecture in VHDL, as described in the book "Introduction to Computing Systems by P&P".

💻 8-bit MISC processor with pipelining.

DSCP is a dynamic secure cache partitioning implementation on gem5. The code includes a ScatterCache (USENIX SECURITY'19) variant and it is partially available to reproduce set partitioning.

[2009 – 2012] MDSP: functional simulation of a Multimedia Digital Signal Processor

This is a repository exclusively created for providing open source verilog codes for various processor microarchitectures and various programming language based codes for research purpose

A cross platform Redis Module Example that warns and uses the optimized functions based on instruction set extensions available and or microarchitecture

A pedagogical processor on FPGA, developed at NIIT University.

💻 Simple accumulator-based 4-bit processor.

A real time computing machine

Presentation about software-based Micro-architectural Side-Channel attacks.