mlir

MLIR mainline added the ability to synthesize get/setters with a properly camel cased and get/set-prefixed name, see this patch and this announcement.

We should do a merge from MLIR mainline to get this, and then adopt it in the CIRCT dialects

It needs to check that the contracting dimensions are the same size.

@honglh

@honglh added optimized kernels for ARM32 in #432. It would be great if we could add support for bitpacked activations to them to match the AArch64 optimized bgemm kernels.

In test/create-cores/test_dma1.mlir, -aie-lower-memcpy convert

  AIE.memcpy @token0(1, 2) (%t11 : <%buf0, 0, 256>, %t22 : <%buf1, 0, 256>) : (memref<256xi32>, memref<256xi32>)
  AIE.memcpy @token1(1, 2) (%t11 : <%buf0, 0, 256>, %t33 : <%buf2, 0, 256>) : (memref<256xi32>, memref<256xi32>)

to (only shows the %t11 side)

  %2 = AIE.mem(%0) {
    %15 = AIE.dmaStart(MM2S0, ^bb1

Sep	OCT	Nov
	17
2020	2021	2022

mlir

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iml130 / mlir-emitc

jmgorius / mlir-standalone-template

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Lewuathe / mlir-hello

samolisov / bazel-llvm-bridge

iml130 / iree-template-cpp

opencompl / lean-mlir

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songwu0813 / HTM

sifive / chisel-circt-demo

schweitzpgi / obsolete-f18

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