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The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Verilog 501 183 Built by @agorararmard @ax3ghazy @donn @tgingold @Manarabdelaty 0 stars today
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efabless / caravel

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

Verilog 14 11 Built by @RTimothyEdwards @Manarabdelaty @jeffdi @marwaneltoukhy @d-m-bailey 0 stars today