processor-architecture

Processor Counter Monitor

GPGPU microprocessor architecture

CoreFreq is a CPU monitoring software designed for the 64-bits Processors.

💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/

WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]

SST Architectural Simulation Components and Libraries

Super scalar Processor design

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

Sunflower Full-System Hardware Emulator and Physical System Simulator for Sensor-Driven Systems. Built-in architecture modeling of Hitachi SH (j-core), RISC-V, and more.

A collection of my cources, lectures, articles and presentations

Modular Graphical Simulator for Teaching Microprogramming

A simulation of the Tomasulo algorithm, a hardware algorithm for out-of-order scheduling and execution of computer instructions, written in C++.

Single Bus Processor - Summer Project 2016

Flexible functional simulator and assembler for user-defined architectures

CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] <Semester IV>

Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic

CS 552 term project : functional design of a microprocessor called the WISC-SP13

💻 MIPS Pipeline Processor simulator

Microprocessor without Interlocked Pipeline Stages with the extra JR, DIV and MFLO instructions implemented.

A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines

An 8-bit processor in VHDL based on a simple instruction set

A Three Stage Pipeline 16-bit processor implemented in Verilog

Open source ISA | Useful in co-processors/CISC add-ons, and limitless code compatibility

MIPS Pipelined CPU simulation using VHDL language

Implementation of a soft-core CPU and an assembler

Continuation of a functional Tomasulo out-of-order processor, with a cache prefetcher and replacement policy. Implements most of the RV32I ISA.

Sextium® III processor implemented in Verilog