analogdevicesinc / hdl
HDL libraries and projects
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HDL libraries and projects
The USRP™ Hardware Driver Repository
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
PicoRV32 - A Size-Optimized RISC-V CPU
Verilog AXI components for FPGA implementation
Plugins for Yosys developed as part of the F4PGA project.
Verilog Ethernet components for FPGA implementation
Verilog configurable cache
Verilog behavioral description of various memories