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525 public repositories
matching this topic...
☔️ interface for parsing, inspecting, transforming, and serializing content through syntax trees
Updated
Mar 8, 2022
JavaScript
Native Operating System and Hardware Information
A PDF processor written in Go.
Processor Counter Monitor
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
A list of ICs and IPs for AI, Machine Learning and Deep Learning.
CoreFreq is a CPU monitoring software designed for the 64-bits Processors.
Mixin is a trait/mixin and bytecode weaving framework for Java using ASM
Updated
Feb 28, 2022
Java
🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Updated
Jan 27, 2022
SystemVerilog
Cross-platform process cpu % and memory usage of a PID
Updated
Apr 8, 2022
JavaScript
RISC-V processor emulator written in Rust+WASM
Updated
Aug 22, 2021
Rust
Updated
May 26, 2022
Assembly
A feature rich code block preprocessing tool.
Updated
Aug 18, 2018
JavaScript
A Forth CPU and System on a Chip, based on the J1, written in VHDL
Updated
Mar 22, 2022
VHDL
Jest HTML Reporter and Results Processor
Updated
Jun 3, 2022
TypeScript
Jest test results processor for generating a summary in HTML
Updated
Jun 3, 2022
TypeScript
A simple RISC-V processor for use in FPGA designs.
A markdown processor written in Go. built for fun.
Install ioquake3 on macos in one command (M1 native support)
Updated
Nov 28, 2021
Shell
💻 A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
Updated
Nov 23, 2021
VHDL
Modern CSS to all browsers
Updated
Feb 28, 2020
JavaScript
Configure multiple loggers and handlers in the blink of an eye
Updated
May 21, 2021
SystemVerilog
AutoPkg recipes all the way from Seattle, WA.
Updated
May 12, 2022
Shell
SDK for Greenwaves Technologies' GAP8 IoT Application Processor
Intel(R) Xeon(R) Processor Max Effort Turbo Boost UEFI DXE driver
A VSP; run your encrypted C code AS IS!
[WIP] Web word processor for 2Tale Writer's Portal.
Updated
Feb 12, 2022
TypeScript
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Currently we don't reset registers or we use
:=initalisers when defining signals.This works ok in FPGAs and ghdl sim but sucks for ASIC and gate level sim as it causes a lot of X state propagation issues.
Scrub all of the code to add resets to register state.