verilog

A professional collaborative platform for embedded development 👽

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

A FPGA friendly 32 bit RISC-V CPU implementation

GPGPU microprocessor architecture

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

❄️ Visual editor for open FPGA boards

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

Haskell to VHDL/Verilog/SystemVerilog compiler

Scala based HDL

HDL libraries and projects

A repository of gate-level simulators and tools for the original Game Boy.

PlatformIO IDE for VSCode: The next generation integrated development environment for IoT

Package manager and build abstraction tool for FPGA/ASIC development

A small, light weight, RISC CPU soft core

SERV - The SErial RISC-V CPU

Must-have verilog systemverilog modules

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Hardware Description Languages

This project will compile verilog (a hardware description language) into factorio blueprints.

OpenROAD's unified application implementing an RTL-to-GDS Flow

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

🌱 Open source ecosystem for open FPGA boards

RISC-V CPU Core (RV32IM)

SCR1 is a high-quality open-source RISC-V MCU core in Verilog