chipsalliance / yosys-f4pga-plugins
Plugins for Yosys developed as part of the F4PGA project.
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Plugins for Yosys developed as part of the F4PGA project.
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
HDL libraries and projects
Wraps the NVDLA project for Chipyard integration
PicoRV32 - A Size-Optimized RISC-V CPU
BaseJump STL: A Standard Template Library for SystemVerilog
Verilog Ethernet components for FPGA implementation
Verilog AXI components for FPGA implementation
Bakraid, Batrider, Garegga, Kingdom Grandprix & Sorcer Striker MiSTer Cores
A template for getting started with FPGA core development
TangPrimer-20K-example project
Must-have verilog systemverilog modules
The USRP™ Hardware Driver Repository