lowRISC / opentitan
OpenTitan: Open source silicon root of trust
| Jul | AUG | Sep |
| 24 | ||
| 2021 | 2022 | 2023 |
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OpenTitan: Open source silicon root of trust
SystemVerilog modules and classes commonly used for verification
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
RISC-V Debug Support for our PULP RISC-V Cores
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.