RISC-V architect, SiFive co-founder, Duke and Cal alum
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Activity overview
Contributed to
riscv-software-src/riscv-isa-sim,
riscv/riscv-isa-manual,
riscv/riscv-opcodes
and 19 other
repositories
Contribution activity
March 2023
Created 11 commits in 3 repositories
Created a pull request in riscv-software-src/riscv-isa-sim that received 13 comments
Don't issue misaligned or non-power-of-2 MMIO accesses
Rather than requiring each MMIO device to support arbitrary sizes and alignments, decompose misaligned loads and stores in such a way as to guarant…
+40
−21
•
13
comments
Opened 1 other pull request in 1 repository
riscv-software-src/riscv-isa-sim
1
merged
Reviewed 5 pull requests in 2 repositories
riscv-software-src/riscv-isa-sim
4 pull requests
riscv-software-src/riscv-tests
1 pull request
1
contribution
in private repositories
Mar 3






