analogdevicesinc / hdl
HDL libraries and projects
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HDL libraries and projects
BaseJump STL: A Standard Template Library for SystemVerilog
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
The USRP™ Hardware Driver Repository
HDMI to whatever adapter
Must-have verilog systemverilog modules
Plugins for Yosys developed as part of the F4PGA project.
Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
PicoRV32 - A Size-Optimized RISC-V CPU