lowRISC / opentitan
OpenTitan: Open source silicon root of trust
| Jun | JUL | Aug |
| 14 | ||
| 2022 | 2023 | 2024 |
COLLECTED BY
Collection: github.com

{{ message }}
See what the GitHub community is most excited about today.
OpenTitan: Open source silicon root of trust
A simple parametrizable doorbell based mailbox
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Common SystemVerilog components
Pipelines the AXI path with FIFOs
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.