EttusResearch / uhd
The USRP™ Hardware Driver Repository
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analogdevicesinc / hdl
HDL libraries and projects
The-OpenROAD-Project / OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
linuxbest / lzs
an open source lzs hardware & software
pConst / basic_verilog
Must-have verilog systemverilog modules
alexforencich / verilog-ethernet
Verilog Ethernet components for FPGA implementation
alexforencich / verilog-axi
Verilog AXI components for FPGA implementation
T-head-Semi / openc906
OpenXuantie - OpenC906 Core
T-head-Semi / opene902
OpenXuantie - OpenE902 Core
The-OpenROAD-Project / OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
aolofsson / oh
Verilog library for ASIC and FPGA designers
The-OpenROAD-Project / OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
google / CFU-Playground
Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.
RapidSilicon / litex_reference_designs
Litex Reference Designs provides reference designs created out of IP Catalog using Litex integration capabilities.
YosysHQ / picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
chipsalliance / yosys-f4pga-plugins
Plugins for Yosys developed as part of the F4PGA project.
efabless / caravel_user_project
IObundle / iob-cache
Verilog configurable cache
