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===XAP3=== |
===XAP3=== |
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XAP3 was designed at Cambridge Consultants in 2003 in response to a project requirement for a 32-bit processor. The project demanded a low cost and low energy ASIC implementation using modern [[CMOS]] semiconductor process technologies at 0.13 micrometre and below. This led Cambridge Consultants’ engineers to make certain design decisions including the use of a |
XAP3 was designed at Cambridge Consultants in 2003 in response to a project requirement for a 32-bit processor. The project demanded a low cost and low energy ASIC implementation using modern [[CMOS]] semiconductor process technologies at 0.13 micrometre and below. This led Cambridge Consultants’ engineers to make certain design decisions including the use of a [[Von Neumann architecture|Von Neumann]], unified data and address bus that enabled both the program's instructions and constants data to be held in a single on-chip memory. The program memory was to be either [[Flash memory|Flash]] or one-time programmable [[EPROM]] and ASIC design is considerably simplified if a single memory is used without the need to pre-determine the split between instructions and fixed data. The XAP3's instruction set design also focussed on high code density to reduce the size of the program memory, thereby reducing cost and also the energy consumed by instruction fetches. |
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===XAP4=== |
===XAP4=== |
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The XAP processor is a RISC processor architecture developed by Cambridge Consultants Ltd since 1994. XAP processors are a family of 16-bit and 32-bit cores, all of which are intended for use in an application-specific integrated circuitorASIC chip design. XAP processors were designed for use in mixed-signal integrated circuits for sensororwireless applications including Bluetooth, ZigBee, GPS, RFIDorNear Field Communication chips. Typically these integrated circuits are used in low cost, high volume products that are battery-powered and must have low energy consumption. There are other applications where XAP processors have been used to good effect, such as wireless sensor networks and medical devices, e.g. hearing aids.
The first XAP processor was XAP1, designed in 1994 and used for a number of wireless and sensor ASIC projects at Cambridge Consultants. It was a very small, 3,000-gate, Harvard architecture, 16-bit processor with a 16-bit data bus and an 18-bit instruction bus intended for running programs stored in on-chip read-only memory or ROM. Data and instructions were each addressed by separate 16-bit address bus.
A more powerful XAP2 was developed and used from 1999. It also had a Harvard architecture and 16-bit data, and it adopted a more conventional 16-bit instruction width suitable for program storage in Flash or other off-chip memories. Large programs were accommodated by a 24-bit address bus for instructions and there was a 16-bit address bus for data. XAP2 was a 12,000-gate processor with support for interrupts and a software tool chain including a C compiler and the XAPASM assembler for its assembly language. XAP2 was also used in Cambridge Consultants' ASIC designs and it was also provided to other semiconductor companies as a semiconductor intellectual property core, or IP core.
XAP2 was adopted by three fabless semiconductor companies that emerged from Cambridge Consultants: CSR plc (Cambridge Silicon Radio) is the main provider of Bluetooth chips for mobile phones and headsets; Ember Corporation is a leading supplier of ZigBee chips; and Cyan Technology supplies XAP2-powered microcontrollers. As a consequence, and combined with other licensees and Cambridge Consultants’ ASIC projects, there are now over one billion (1,000 million) XAP processors in use worldwide.
XAP3 was designed at Cambridge Consultants in 2003 in response to a project requirement for a 32-bit processor. The project demanded a low cost and low energy ASIC implementation using modern CMOS semiconductor process technologies at 0.13 micrometre and below. This led Cambridge Consultants’ engineers to make certain design decisions including the use of a Von Neumann, unified data and address bus that enabled both the program's instructions and constants data to be held in a single on-chip memory. The program memory was to be either Flash or one-time programmable EPROM and ASIC design is considerably simplified if a single memory is used without the need to pre-determine the split between instructions and fixed data. The XAP3's instruction set design also focussed on high code density to reduce the size of the program memory, thereby reducing cost and also the energy consumed by instruction fetches.
In 2005, further project requirements saw a new 16-bit processor, the XAP4, designed to supersede the XAP2 taking into account the experience gained on XAP3 and the evolving requirements of ASIC designs. XAP4 is a very small, 12,000-gate, Von Neumann bus, 16-bit processor core capable of addressing a total of 64 kBytes of memory for programs, data and peripherals. It offers high code density combined with good performance in the region of 50 Dhrystone MIPS when clocked at 80 MHz. XAP4 was designed for use in modern ASIC or microcontroller applications capable of processing real-world data captured by an Analog to digital converter (ADC) or similar sources. The processor's 16-bit integer word supports the precision of most ADCs without carrying the overhead of a 32-bit processor. XAP4 also offers a migration path from 8-bit processors, such as 8051, in applications that need increased performance and program size, but cannot justify the cost and overhead of a 32-bit processor.
Development of an extended version of this architecture commenced in 2006 and resulted in the XAP5, which was announced in July 2008. XAP5 is a 16-bit processor with a 24-bit address bus making it capable of running programs from memory up to 16 MBytes. XAP4 and XAP5 are both implemented with a two-stage instruction pipeline, which maximises their performance when clocked at low frequencies. This is tailored to the requirements of small, low-energy ASICs as it minimises processor hardware size (the XAP5 core uses 18,000-gates), and it fits designs that are clocked relatively slowly to reduce an ASIC's dynamic power consumption and run programs direct from Flash or OTP memory that has a slow access time. Typical clock speeds for XAP5 are in the range of 16 to 100 MHz on a 0.13 process. XAP5 has particular design features making it suitable for executing programs from Flash including a Vector Pointer and an Address Translation Window, which combine to allow in-place execution of programs and relocation of programs regardless of where they are stored in physical memory.
XAP3, XAP4 and XAP5 are all designed with a load-store RISC architecture that is complemented with multi-cycle instructions for multiplication, division, block copy/store and function entry/exit for maximum efficiency. Cambridge Consultants’ engineers recognised the requirement for these processors to run real-time operating systems capable of handling pre-emptive events and with a fast interrupt response. Consequently the processors are designed with hardware and instruction set support for protected software operating modes that partition user code from privileged operating system and interrupt handler code. The XAP processor hardware manages the mode transitions and call stack in response to events and this approach ensures a fast and deterministic interrupt response. The protected operating modes enable a system on a chip to be designed that is a secure or trustworthy system and offers high availability.
The current XAP processors are designed using the Verilog hardware description language and provided as RTL code ready for logic simulation and logic synthesis with a test bench. They are supported with Cambridge Consultants’ xIDE software development tools and SIF debug technology. These processors and tools enable functional verification and software verification that reduces the project risk, accelerates time-scales and cuts cost of ownership, especially for software engineering.
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Reduced instruction set computer (RISC) architectures
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