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The Ultra-Low Power RISC Core

open-source IEEE802.11/Wi-Fi baseband chip/FPGA design

GPGPU microprocessor architecture

Haskell to VHDL/Verilog/SystemVerilog compiler

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A FPGA friendly 32 bit RISC-V CPU implementation

❄️ Visual editor for open FPGA boards

HDL libraries and projects

A small, light weight, RISC CPU soft core

Scala based HDL

PlatformIO IDE for VSCode: The next generation integrated development environment for IoT

PlatformIO IDE for Atom: The next generation integrated development environment for IoT

A Just-In-Time Compiler for Verilog from VMware Research

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

mor1kx - an OpenRISC 1000 processor IP core

🌱 Open source ecosystem for open FPGA boards

Hardware Description Languages

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

Repository for basic (and not so basic) Verilog blocks with high re-use potential

The OpenPiton Platform

CNN acceleration on virtex-7 FPGA with verilog HDL

An abstraction library for interfacing EDA tools

Various HDL (Verilog) IP Cores