Contents

Memory rank

Details[edit]

The term rank was created and defined by JEDEC, the memory industry standards group. On a DDR, DDR2, or DDR3 memory module, each rank has a 64-bit-wide data bus (72 bits wide on DIMMs that support ECC). The number of physical DRAMs depends on their individual widths. For example, a rank of ×8 (8-bit wide) DRAMs would consist of eight physical chips (nine if ECC is supported), but a rank of ×4 (4-bit wide) DRAMs would consist of 16 physical chips (18, if ECC is supported). Multiple ranks can coexist on a single DIMM. Modern DIMMs can for example feature one rank (single rank), two ranks (dual rank), four ranks (quad rank), or eight ranks (octal rank).^{[citation needed]}

There is only a little difference between a dual rank UDIMM and two single-rank UDIMMs in the same memory channel, other than that the DRAMs reside on different PCBs. The electrical connections between the memory controller and the DRAMs are almost identical (with the possible exception of which chip selects go to which ranks). Increasing the number of ranks per DIMM is mainly intended to increase the memory density per channel. Too many ranks in the channel can cause excessive loading and decrease the speed of the channel. Also some memory controllers have a maximum supported number of ranks. DRAM load on the command/address (CA) bus can be reduced by using registered memory.^{[citation needed]}

Predating the term rank (sometimes also called row) is the use of single-sided and double-sided modules, especially with SIMMs. While most often the number of sides used to carry RAM chips corresponded to the number of ranks, sometimes they did not. This could lead to confusion and technical issues.^[2][3]

Performance of multiple rank modules[edit]

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There are several effects to consider regarding memory performance in multi-rank configurations:

• Multi-rank modules allow several open DRAM pages (row) in each rank (typically eight pages per rank). This increases the possibility of getting a hit on an already open row address. The performance gain that can be achieved is highly dependent on the application and the memory controller's ability to take advantage of open pages.^{[citation needed]}
• Multi-rank modules have higher loading on the data bus (and on unbuffered DIMMs the CA bus as well). Therefore if more than dual rank DIMMs are connected in one channel, the speed might be reduced.^{[citation needed]}
• Subject to some limitations, ranks can be accessed independently, although not simultaneously as the data lines are still shared between ranks on a channel. For example, the controller can send write data to one rank while it awaits read data previously selected from another rank. While the write data is consumed from the data bus, the other rank could perform read-related operations such as the activation of a row or internal transfer of the data to the output drivers. Once the CA bus is free from noise from the previous read, the DRAM can drive out the read data. Controlling interleaved accesses like so is done by the memory controller.^{[citation needed]}
• There is a small performance reduction for multi-rank systems as they require some pipeline stalls between accessing different ranks. For two ranks on a single DIMM it might not even be required, but this parameter is often programmed independently of the rank location in the system (if on the same DIMM or different DIMMs). Nevertheless, this pipeline stall is negligible compared to the aforementioned effects.^{[citation needed]}

See also[edit]

• Memory geometry

References[edit]

Bibliography[edit]

• Balasubramonian, Rajeev (May 2022). Innovations in the Memory System. Springer. ISBN 9783031017636.
• Bruce, Jacob; Wang, David; Ng, Spencer (2008). Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann Publishers. ISBN 978-0-12-379751-3.