In order to compete with Intel's Advanced Programmable Interrupt Controller (APIC), which had enabled the first Intel 486-based multiprocessor systems, in early 1995 AMD and Cyrix proposed as somewhat similar-in-purpose OpenPIC architecture supporting up to 32 processors.[1] The OpenPIC architecture had at least declarative support from IBM and Compaq around 1995.[2] No x86 motherboard was released with OpenPIC however.[3] After the OpenPIC's failure in the x86 market, AMD licensed the Intel APIC Architecture for its AMD Athlon and later processors.
IBM however developed their Multiprocessor Interrupt Controller (MPIC) based on the OpenPIC register specification.[4] In the reference IBM design, the processors share the MPIC over a DCR bus, with their access to the bus controlled by a DCR Arbiter. MPIC supports up to four processors and up to 128 interrupt sources.[4] Through various implementations, the MPIC was included in PowerPC reference designs and some retail computers.
IBM used a MPIC based on OpenPIC 1.0 in their RS/6000 F50 and one based on OpenPIC 1.2 in their RS/6000 S70. Both of these systems also used a dual 8259 on their PCI-ISA bridges.[5] An IBM MPIC was also used in the RS/6000 7046 Model B50.[6]
The Apple Hydra Mac I/O (MIO) chip (from the 1990s classic Mac OS era) implemented a MPIC alongside a SCSI controller, ADB controller, GeoPort controller, and timers.[7] The Apple implementation of "Open PIC" (as the Apple documentation of this era spells it) in their first MIO chip for the Common Hardware Reference Platform was based on version 1.2 of the register specification and supported up to two processors and up to 20 interrupt sources.[8] A MPIC was also incorporated in the newer K2 I/O controller used in the Power Mac G5s.[9][10]
Freescale also uses a MPIC ("compatible with the Open PIC") on all its PowerQUICC and QorIQ processors.[11] The Linux Kernel-based Virtual Machine (KVM) supports a virtualized MPIC with up to 256 interrupts, based on the Freescale variants.[12]
