Jump to content
 







Main menu
   


Navigation  



Main page
Contents
Current events
Random article
About Wikipedia
Contact us
Donate
 




Contribute  



Help
Learn to edit
Community portal
Recent changes
Upload file
 








Search  

































Create account

Log in
 









Create account
 Log in
 




Pages for logged out editors learn more  



Contributions
Talk
 



















Contents

   



(Top)
 


1 See also  





2 References  














Registermemory architecture






Català
Čeština
Español
فارسی
 

Edit links
 









Article
Talk
 

















Read
Edit
View history
 








Tools
   


Actions  



Read
Edit
View history
 




General  



What links here
Related changes
Upload file
Special pages
Permanent link
Page information
Cite this page
Get shortened URL
Download QR code
Wikidata item
 




Print/export  



Download as PDF
Printable version
 
















Appearance
   

 






From Wikipedia, the free encyclopedia
 


Incomputer engineering, a register–memory architecture is an instruction set architecture that allows operations to be performed on (or from) memory, as well as registers.[1] If the architecture allows all operands to be in memory or in registers, or in combinations, it is called a "register plus memory" architecture.[1]

In a register–memory approach one of the operands for operations such as the ADD operation may be in memory, while the other is in a register. This differs from a load–store architecture (used by RISC designs such as MIPS) in which both operands for an ADD operation must be in registers before the ADD.[1]

An example of register-memory architecture is Intel x86.[1] Examples of register plus memory architecture are:

See also[edit]

References[edit]

  1. ^ a b c d Michael J. Flynn (1995). Computer architecture: pipelined and parallel processor design. pp. 9–12. ISBN 0867202041.
  • ^ IBM System/360 Principles of Operation (PDF). IBM. September 1968. A22-6821-7.
  • ^ IBM Enterprise Systems Architecture/370 Principles of Operation (PDF). IBM. August 1988. SA22-7200-0.
  • ^ z/Architecture Principles of Operation (PDF). IBM. September 2017. SA22-7832-11.
  • ^ pdp11 processor handbook pdp11/04/34a/44/60/70 (PDF). DEC. 1979. Retrieved 13 November 2015.
  • ^ VAX Architecture Reference Manual (PDF). Digital Equipment Corporation. 1987. EY-3459E-DP.
  • ^ MC68020 32-Bit Microprocessor User's Manual (PDF). Motorola. 1984. MC68020UM[ADI).

  • Retrieved from "https://en.wikipedia.org/w/index.php?title=Register–memory_architecture&oldid=1214388349"

    Category: 
    Computer architecture
    Hidden categories: 
    Articles with short description
    Short description is different from Wikidata
     



    This page was last edited on 18 March 2024, at 17:22 (UTC).

    Text is available under the Creative Commons Attribution-ShareAlike License 4.0; additional terms may apply. By using this site, you agree to the Terms of Use and Privacy Policy. Wikipedia® is a registered trademark of the Wikimedia Foundation, Inc., a non-profit organization.



    Privacy policy

    About Wikipedia

    Disclaimers

    Contact Wikipedia

    Code of Conduct

    Developers

    Statistics

    Cookie statement

    Mobile view



    Wikimedia Foundation
    Powered by MediaWiki