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Contents

   



(Top)
 


1 Changes  





2 CPUs with SSE3  





3 New instructions  



3.1  Common instructions  





3.2  Intel instructions  







4 External links  














SSE3






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From Wikipedia, the free encyclopedia
 


This is an old revision of this page, as edited by 139.80.48.19 (talk)at00:48, 18 May 2011 (Clarified "pni" flag). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.
(diff)  Previous revision | Latest revision (diff) | Newer revision  (diff)

SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revision of their Pentium 4 CPU. In April 2005, AMD introduced a subset of SSE3 in revision E (Venice and San Diego) of their Athlon 64 CPUs. The earlier SIMD instruction sets on the x86 platform, from oldest to newest, are MMX, 3DNow! (developed by AMD), SSE and SSE2.

SSE3 contains 13 new instructions over SSE2. On UNIX-like systems, a CPU can be identified as having SSE3 by the presence of the flag "pni" in /proc/cpuinfo.

Changes

The most notable change is the capability to work horizontally in a register, as opposed to the more or less strictly vertical operation of all previous SSE instructions. More specifically, instructions to add and subtract the multiple values stored within a single register have been added. These instructions simplify the implementation of a number of DSP and 3D operations. There is also a new instruction to convert floating point values to integers without having to change the global rounding mode, thus avoiding costly pipeline stalls. Finally, the extension adds LDDQU, an alternative misaligned integer vector load that has better performance on NetBurst based platforms for loads that cross cacheline boundaries.

CPUs with SSE3

New instructions

Common instructions

Arithmetic

AOS ( Array Of Structures )

Intel instructions

External links


Retrieved from "https://en.wikipedia.org/w/index.php?title=SSE3&oldid=429651286"

Categories: 
Parallel computing
X86 instructions
SIMD computing
 



This page was last edited on 18 May 2011, at 00:48 (UTC).

This version of the page has been revised. Besides normal editing, the reason for revision may have been that this version contains factual inaccuracies, vandalism, or material not compatible with the Creative Commons Attribution-ShareAlike License.



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