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(Top) 1 x86 architecture processors 1.1 Intel 1.2 AMD 2 References 3 External links

Intel SHA extensions

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Intel SHA Extensions are a set of extensions to the x86 instruction set architecture which support hardware accelerationofSecure Hash Algorithm (SHA) family. It was introduced in 2013. Instructions for SHA-512 will be introduced in Arrow Lake and Lunar Lake in 2024.

The original SSE-based extensions added four instructions supporting SHA-1 and three for SHA-256. AVX-based versions are also available with a V prefix.

SHA-1: SHA1RNDS4, SHA1NEXTE, SHA1MSG1, SHA1MSG2
SHA-256: SHA256RNDS2, SHA256MSG1, SHA256MSG2

The AVX-based extensions added three for SHA-512.

VSHA512RNDS2, VSHA512MSG1, VSHA512MSG2

x86 architecture processors[edit]

Intel[edit]

The following Intel processors support the original SHA instruction set:

Intel Goldmont (and later Atom microarchitectures) processors.^[1]
Intel Ice Lake (and later) processors.^[2]
Intel Rocket Lake (and later) processors.

The following Intel processors will support the newer SHA-512 instruction set:

Intel Arrow Lake and Lunar Lake processors.

AMD[edit]

Several AMD processors support the original SHA instruction set:

AMD Zen (and later) processors.^[3]

References[edit]

^ "Goldmont - Microarchitectures - Intel - WikiChip". en.wikichip.org. Retrieved 2020-06-26.

^ "Ice Lake (client) - Microarchitectures - Intel - WikiChip". en.wikichip.org. Retrieved 2020-06-26.

^ "Zen - Microarchitectures - AMD - WikiChip". en.wikichip.org. Retrieved 2020-06-26.

External links[edit]

New Instructions Supporting the Secure Hash Algorithm on Intel® Architecture Processors
Intel Instruction Set Architecture Extensions
"Intel Architecture Instruction Set Extensions Programming Reference" (PDF). Archived from the original (PDF) on 2013-09-29., Chapter 8

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BCD oriented (4-bit)	4004 (1971) 4040 (1974)
pre-x86 (8-bit)	8008 (1972) 8080 (1974) 8085 (1977)
Early x86 (16-bit)	8086 (1978) 8088 (1979) 80186 (1982) 80188 (1982) 80286 (1982)
x87 (external FPUs)	8/16-bit databus 8087 (1980) 16-bit databus 80C187 80287 80387SX 32-bit databus 80387DX 80487
IA-32 (32-bit x86)	i386 SX 376 EX i486 SX DX2 DX4 SL RapidCAD OverDrive A100/A110 Atom CE SoC Celeron (1998) M D (2004) Pentium Original i586 OverDrive Pro II III 4 M Dual-Core Core Xeon P6-based NetBurst-based Core-based Quark Tolapai
x86-64 (64-bit)	Atom SoC CE Celeron D Dual-Core Pentium 4 D Extreme Edition Dual-Core Core 2 1st gen 2nd gen 3rd gen 4th gen 5th gen 6th gen 7th gen 8th gen 9th gen 10th gen 11th gen M Xeon Nehalem-based Sandy Bridge-based Ivy Bridge-based Haswell-based Broadwell-based Skylake-based
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v t e Instruction set extensions
SIMD (RISC)	Alpha MVI ARM NEON SVE MIPS MDMX MIPS-3D MXU MIPS SIMD PA-RISC MAX Power ISA VMX SPARC VIS
SIMD (x86)	MMX (1996) 3DNow! (1998) SSE (1999) SSE2 (2001) SSE3 (2004) SSSE3 (2006) SSE4 (2006) SSE5 ~~(2007)~~ AVX (2008) F16C (2009) XOP (2009) FMA (FMA4: 2011, FMA3: 2012) AVX2 (2013) AVX-512 (2015) AMX (2022) AVX10 (2023)
Bit manipulation	BMI (ABM: 2007, BMI1: 2012, BMI2: 2013, TBM: 2012) ADX (2014)
Compressed instructions	Thumb MIPS16e ASE RVC
Security and cryptography	PadLock (2003) AES-NI (2008); ARMv8 also has AES instructions CLMUL (2010) RDRAND (2012) SHA (2013) MPX (2015) SGX (2015) TDX (2021)
Transactional memory	TSX (2013) ASF
Virtualization	VT-x (2005) AMD-V (2006) VT-d (AMD-Vi)
Suspended extensions' dates are ~~struck through~~.