VIA PadLock is a central processing unit (CPU) instruction set extension to the x86 microprocessor instruction set architecture (ISA) found on processors produced by VIA Technologies and Zhaoxin. Introduced in 2003 with the VIA Centaur CPUs, the additional instructions provide hardware-accelerated random number generation (RNG), Advanced Encryption Standard (AES), SHA-1, SHA256, and Montgomery modular multiplication.[1][2]
The PadLock instruction set can be divided into four subsets:[1]
XSTORE: Store Available Random Bytes (aka XSTORERNG)REP XSTORE: Store ECX Random BytesREP XCRYPTECB: Electronic code bookREP XCRYPTCBC: Cipher Block ChainingREP XCRYPTCTR: Counter Mode (ACE2)REP XCRYPTCFB: Cipher Feedback ModeREP XCRYPTOFB: Output Feedback ModeREP XSHA1: Hash Function SHA-1REP XSHA256: Hash Function SHA-256REP MONTMUL
The padlock capability is indicated via a CPUID instruction with EAX = 0xC0000000. If the resultant EAX >= 0xC0000001, the CPU is aware of Centaur features. An additional request with EAX = 0xC0000001 then returns PadLock support in EDX. The padlock capability can be toggled on or off with MSR 0X1107.[1]
VIA PadLock found on some Zhaoxin CPUs have SM3 hashing and SM4 block cipher added.[3]
padlock(4) – FreeBSD Kernel Interfaces Manual
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| SIMD (RISC) |
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| SIMD (x86) |
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| Bit manipulation |
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| Compressed instructions |
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| Security and cryptography |
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| Transactional memory |
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| Virtualization |
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Suspended extensions' dates are | |
