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In lower power systems, Hierarchical Value Cache refers to the hierarchical arrangement of Value Caches (VCs) in such a fashion that lower level VCs observe higher hit-rates, but undergo more switching activity on VC hits.
The organization is similar to Memory Hierarchy, where lower-level caches enjoy higher hit rates, but longer hit latencies. The architecture for Hierarchical Value Cache is mainly organized along two approaches: Hierarchical Unified Value Cache (HUVC) and Hierarchical Combinational Value Cache (HCVC).[1]
This architecture of Value Cache employs all value caches storing full data values, with larger value caches in the lower levels of the hierarchy. This architecture suffers from high area overhead, but reduces the bus switching activity.
The cache in HUVC in managed by LRU policy, with each VC storing 32-bit values. For incoming data, it is simultaneously checked with the VC on each level, with the uppermost VC hit getting encoded. Each hit at the ith level of the HUVC incurs i bits switching activity. By switching any bit of 32-bit data bus, we can get (32!)/((32-i)!i!) numbers. That is, we could have (32!)/((32-i)!i!) entries. However, it would require complicated logic to map VC indexes to bus values. For easy VC index encoding, we partition the data bus into i segments and switch one bit in each segment.
Thus, the HUVC scheme requires n control signals, where n is the depth of the VC hierarchy. The i-th control signal switched to indicate that the VC of level i hits.
For 4-level HUVC, and 32-bit data bus, the total VC size is 22.4KB. The size of the VC is too large to be feasible in practice.
In HCVC, level i contains 2^(i-1) VCs that store only partial values, instead of full values as in HUVC.
Except the case of first level, all VCs in HCVC store partial data values only. 2^(i-1) segments are generated by partitioning the data values, and each VC stores one data segment. Similar to the HUVC, the incoming data is simultaneously checked with the VC on each level, with the uppermost VC hit getting encoded.
The HCVC scheme requires n Control signals, where i is the number of VCs. The i-th control signal is switched to indicate the Formula VC hit. The total VC size of the i-th level is 32/(2^(i-1)) words. For 4-level HCVC with 32-bit data bus, the total VC size is only 240 bytes.
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