J u m p t o c o n t e n t
M a i n m e n u
M a i n m e n u
N a v i g a t i o n
● M a i n p a g e ● C o n t e n t s ● C u r r e n t e v e n t s ● R a n d o m a r t i c l e ● A b o u t W i k i p e d i a ● C o n t a c t u s ● D o n a t e
C o n t r i b u t e
● H e l p ● L e a r n t o e d i t ● C o m m u n i t y p o r t a l ● R e c e n t c h a n g e s ● U p l o a d f i l e
S e a r c h
Search
A p p e a r a n c e
● C r e a t e a c c o u n t ● L o g i n
P e r s o n a l t o o l s
● C r e a t e a c c o u n t ● L o g i n
P a g e s f o r l o g g e d o u t e d i t o r s l e a r n m o r e ● C o n t r i b u t i o n s ● T a l k
( T o p )
1 T e c h n o l o g y
2 R e f e r e n c e s
3 E x t e r n a l l i n k s
T o g g l e t h e t a b l e o f c o n t e n t s
T I L E P r o 6 4
1 l a n g u a g e
● C a t a l à
E d i t l i n k s
● A r t i c l e ● T a l k
E n g l i s h
● R e a d ● E d i t ● V i e w h i s t o r y
T o o l s
T o o l s
A c t i o n s
● R e a d ● E d i t ● V i e w h i s t o r y
G e n e r a l
● W h a t l i n k s h e r e ● R e l a t e d c h a n g e s ● U p l o a d f i l e ● S p e c i a l p a g e s ● P e r m a n e n t l i n k ● P a g e i n f o r m a t i o n ● C i t e t h i s p a g e ● G e t s h o r t e n e d U R L ● D o w n l o a d Q R c o d e ● W i k i d a t a i t e m
P r i n t / e x p o r t
● D o w n l o a d a s P D F ● P r i n t a b l e v e r s i o n
A p p e a r a n c e
F r o m W i k i p e d i a , t h e f r e e e n c y c l o p e d i a
The short-pipeline , in-order, three-issue cores implement a VLIW instruction set . Each core has a register file and three functional units: two integer arithmetic logic units and a load–store unit. Each of the cores ("tile") has its own L1 and L2 caches plus an overall virtual L3 cache which is an aggregate of all the L2 caches.[1]
TILEPro 64 has four DDR2 controllers at up to 800MT/s, two 10-gigabit Ethernet XAUI interfaces, two four-lane PCIe interfaces, and a "flexible" input/output interface, which can be software-configured to handle a number of protocols. The processor is fabricated using a 90 nm process and runs at speeds of 600 to 866 MHz.
According to the company, Tilera targets the chip at networking equipment, digital video, and wireless infrastructure markets where the demands for computing processing are high.[2] [3]
TILEPro was supported by the Linux kernel from version 2.6.36 to version 4.16.
Block diagram of the TILEPro 64 Processor Scheme of a TILE of the TILEPro 64 Processor
Technology
[ edit ]
Various sources have stated the specifications of processors in the TILEPro family:
64 RISC processor cores
16 KB
64 KB L2 cache per core
4 MB L3 cache is achieved through the sharing of other tiles L2 caches with hardware-managed coherency
90 nm manufacturing process at TSMC
4 integrated memory controllers supporting DDR2 SDRAM at up to 800MT/s
supports up to 64 GB of attached DDR2 memory
Integrated high-speed I/O
Two 4-lane PCI Express Gen1 interfaces, with root or endpoint capability
Two 10 Gbit/s Ethernet XAUI interfaces
Two 10/100/1000 Mbit/s Ethernet RGMII interfaces
Power consumption in the range of 19 - 23 Watts
The TILEPro family incorporates a number of enhancements over Tilera's first generation TILE64 family:
"Distributed Dynamic Cache" (DDC) system that uses a separate mesh network to manage cache-coherency
"TileDirect" I/O enables direct transfer of network data coherently into the processor caches
Double the L1 instruction cache (from 8 KB to 16 KB ), double the L2 associativity
Memory "striping" on the DDR2 interfaces to balance the loading
Instruction set enhancements for multimedia, unaligned data access, offset load/store instructions and memory access hints
The networking software company 6WIND provides high-performance packet processing software for the TILEPro 64 platform.[4]
References
[ edit ]
^ Demerjian, Charlie (September 22, 2008). "Tilera releases a second 64-core chip" . The Inquirer. Archived from the original on September 25, 2009. {{cite news }}: CS1 maint: unfit URL (link )
^ Demerjian, Charlie (June 23, 2010). "Tilera gets into the cloud server business" . SemiAccurate.
^ http://www.6wind.com/wp-content/uploads/PDF/press/2011/6WIND-announces-availability-of-Tilera-TilePro64-support.pdf [bare URL PDF
External links
[ edit ] R e t r i e v e d f r o m " https://en.wikipedia.org/w/index.php?title=TILEPro64&oldid=1226635329 " C a t e g o r i e s : ● M a n y c o r e p r o c e s s o r s ● V e r y l o n g i n s t r u c t i o n w o r d c o m p u t i n g ● C o m p u t e r - r e l a t e d i n t r o d u c t i o n s i n 2 0 0 8 H i d d e n c a t e g o r i e s : ● C S 1 m a i n t : u n f i t U R L ● A l l a r t i c l e s w i t h b a r e U R L s f o r c i t a t i o n s ● A r t i c l e s w i t h b a r e U R L s f o r c i t a t i o n s f r o m M a r c h 2 0 2 2 ● A r t i c l e s w i t h P D F f o r m a t b a r e U R L s f o r c i t a t i o n s
● T h i s p a g e w a s l a s t e d i t e d o n 3 1 M a y 2 0 2 4 , a t 2 2 : 3 5 ( U T C ) . ● T e x t i s a v a i l a b l e u n d e r t h e C r e a t i v e C o m m o n s A t t r i b u t i o n - S h a r e A l i k e L i c e n s e 4 . 0 ;
a d d i t i o n a l t e r m s m a y a p p l y . B y u s i n g t h i s s i t e , y o u a g r e e t o t h e T e r m s o f U s e a n d P r i v a c y P o l i c y . W i k i p e d i a ® i s a r e g i s t e r e d t r a d e m a r k o f t h e W i k i m e d i a F o u n d a t i o n , I n c . , a n o n - p r o f i t o r g a n i z a t i o n . ● P r i v a c y p o l i c y ● A b o u t W i k i p e d i a ● D i s c l a i m e r s ● C o n t a c t W i k i p e d i a ● C o d e o f C o n d u c t ● D e v e l o p e r s ● S t a t i s t i c s ● C o o k i e s t a t e m e n t ● M o b i l e v i e w
