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XAUI

The purpose of the XGMII Extender, which is composed of an XGXS (XGMII Extender Sublayer) at the MAC end, an XGXS at the PHY end and a XAUI between them, is to extend the operational distance of the XGMII and to reduce the number of interface signals. Applications include extending the physical separation possible between MAC and PHY components in a 10 Gigabit Ethernet system distributed across a circuit board.

Operation[edit]

XGMII Extender has the following characteristics:

• Simple signal mapping to the XGMII
• Independent transmit and receive data paths
• Four lanes conveying the XGMII 32-bit data and control
• Differential signaling with low voltage swing (1600 mV_p-p)
• Self-timed interface allows jitter control to the PCS
• Shared technology with other 10 Gbit/s interfaces
• Shared functionality with other 10 Gbit/s Ethernet blocks
• Utilization of 8b/10b encoding

The following is a list of the major concepts of XGXS and XAUI:

• The optional XGMII Extender can be inserted between the Reconciliation Sublayer and the PHY (physical layer) to transparently extend the physical reach of the XGMII and reduce the interface pin count from 72 to 16.
• The XGMII is organized into four lanes with each lane conveying a data octet or control character on each edge of the associated clock. The source XGXS converts bytes on an XGMII lane into a self clocked, serial, 8b/10b encoded data stream. Each of the four XGMII lanes is transmitted across one of the four XAUI lanes.
• The source XGXS converts XGMII Idle control characters (interframe) into an 8b/10b code sequence. The destination XGXS recovers clock and data from each XAUI lane and deskews the four XAUI lanes into the single-clock XGMII.
• The destination XGXS adds to or deletes from the interframe as needed for clock rate disparity compensation prior to converting the interframe code sequence back into XGMII Idle control characters.
• The XGXS uses the same code and coding rules as the 10GBASE-X PCS and PMA specified in Clause 48 of the IEEE 802.3 Specification.
• Each of the 4 Receive and Transmit lanes operates at a rate of 3.125 Gbit/s.
• Capabilities have been built into XAUI to overcome the inter-lane signal-skewing problems using a type of automatic de-skewing. Signals can be launched at the transmitter end of a XAUI line without precisely matching the routing of the four lanes, and the signals will be automatically de-skewed at the receiver.^[1]

RXAUI[edit]

Reduced Pin eXtended Attachment Unit Interface (RXAUI) is a proprietary modification created by Marvell^[2] and Dune Networks^[3] (later acquired by Broadcom^[4]) aimed to increase the port density by decreasing the interface pin count. The four lanes of the standard XAUI running at 3.125 Gbit/s are replaced by two lanes at 6.25 Gbit/s. Thus 16 pins of an integrated circuit (4 transmit + 4 receive differential pairs) can provide either one XAUI port or two RXAUI ports.

The specification also defines a XAUI to RXAUI adapter, and provides an implementation as Verilog RTL code.^[2] FPGA vendors are offering their own implementations as IP blocks.^[5][6]

Applications[edit]

Intended Use[edit]

The implementation of XAUI as an optional XGMII Extender is primarily intended as a chip-to-chip (integrated circuit to integrated circuit) interface implemented with traces on a printed circuit board. Where the XGMII is electrically limited to distances of approximately 7 cm, the XGMII Extender allows distances up to approximately 50 cm.

Rate of operation[edit]

The XGMII Extender supports the 10 Gbit/s data rate of the XGMII. The 10 Gbit/s MAC data stream is converted into four lanes at the XGMII (by the Reconciliation Sublayer for transmit or the PHY for receive). The byte stream of each lane is 8b/10b encoded by the XGXS for transmission across the XAUI at a nominal rate of 3.125 gigabaud. The XGXS at the PHY end of the XGMII Extender (PHY XGXS) and the XGXS at the RS end (DTE XGXS) may operate on independent clocks.

Allocation of functions[edit]

The XGMII Extender is transparent to the Reconciliation Sublayer and PHY device, and operates symmetrically with similar functions on the DTE transmit and receive data paths. The XGMII Extender is logically composed of two XGXSs interconnected with a XAUI data path in each direction. One XGXS acts as the source to the XAUI data path in the DTE transmit path and as the destination in the receive path. The other XGXS is the destination in the transmit path and source in the receive path. Each XAUI data path is composed of four serial lanes. All specifications for the XGMII Extender are written assuming conversion from XGMII to XAUI and back to XGMII, but other techniques may be employed provided that the result is that the XGMII Extender operates as if all specified conversions had been made. One example of this is the use of the optional XAUI with the 10GBASE-LX4 8b/10b PHY, where the XGXS interfacing to the Reconciliation Sublayer provides the PCS and PMA functionality required by the PHY. An XGXS layer is not required at the PHY end of the XAUI in this case. However, means may still be required to remove jitter introduced on the XAUI in order to meet PHY jitter requirements.

See also[edit]

• Medium Attachment Unit
• Small form-factor pluggable transceiver
• Gigabit interface converter
• List of device bandwidths

References[edit]

External links[edit]

• IEEE Standards' official XAUI documentation
• Full text of the 802.3 standard
• Altera's 10 Gb Ethernet XAUI Solution
• Xilinx's 10 Gb Ethernet XAUI Solution
• Snowbush IP XAUI PHYs
• XAUI interface 10gea whitepaper archived