Contents

Unified Power Format

History[edit]

A Unified Power Format technical committee was formed by the Accellera organization, chaired by Stephen Bailey of Mentor Graphics. As a reaction to the Power Forward Initiative the group was proposed in July 2006 and met on September 13, 2006.^[1] It submitted its first draft in January 2007, and a version 1.0 was approved to be published on February 26, 2007.^[2] Joe Daniels was technical editor.^[3]

Files written to this standard annotate an electric design with the power and power control intent of that design. Elements of that annotation include:

• Power Supplies: supply nets, supply sets, power states
• Power Control: power switches
• Additional Protection: level shifters and isolation
• Memory retention during times of limited power: retention strategies and supply set power states
• Refinable descriptions of the potential power applied to the electronic system: power states, transitions, a set of simstate^{[check spelling]}, power/ground pin type (pg_type) and function attributes of nets, and the -update argument to support the progressive refinement of the power intent.

The standard describes extensions to the Tool Command Language (Tcl): commands and arguments for annotating a design hierarchy which has been read into a tool. Semantics for inferring additional elements in the design from the intent are provided in the standard. Digital designers, IP Block providers, Physical Designers, and Verification engineers make use of this standard language to communicate their design intent and implementation with respect to the variable power of an electronic system.

The Design Automation Standards Committee (DASC) of the IEEE Standards Association sponsored working group 1801, with the project authorization approved on May 7, 2007.^[4][5] Goals included:

• clarify the semantics of the intent - this provides portability of design intent across many vendors tools
• Add support for incremental refinement - Platinum source (constraints) from IP vendors, Golden source (configuration) from IP integrators, and Silicon source (implementation choices) from those that realize the instantiations.
• Add support for bottom up and top down design
• add documentation of the support for wildcard and regular expression selection of design instances
• clarify the differences between ports and pins
• provide for convergence capability from both UPF and Common Power Format of the Silicon Integration Initiative (Si2)

The IEEE group was initially called the "Low Power Study Group". Proposed standards have the letter "P" in front of them (such as P1801), which is removed and replaced with a dash and year when the standard is ratified. Accelera's UPF 1.0 was donated to the IEEE as a basis of this standard in June 2006.^[6]

After reviewing 14 drafts, on March 27, 2009, the "Standard for Design and Verification of Low Power Integrated Circuits" was published as IEEE Std 1801-2009.^[7] It is sometimes called UPF 2.0. Bailey was also chairman of the IEEE group.^[8] Another notable supporter of the standard was Synopsys.^[9] A follow-on project planned to develop a list of frequently asked questions (FAQ) about the specification.^[5]

References[edit]

• 1801-2009 — IEEE Standard for Design and Verification of Low Power Integrated Circuits. 2009. doi:10.1109/IEEESTD.2009.4809845. ISBN 978-0-7381-5929-4.
• 1801-2013 — IEEE Standard for Design and Verification of Low-Power Integrated Circuits. 2013. doi:10.1109/IEEESTD.2013.6521327. ISBN 978-0-7381-8281-0.
• 1801-2015 — IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems. 2016. doi:10.1109/IEEESTD.2016.7445797. ISBN 978-1-5044-0105-0.
• 1801-2018 — IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems. 2019. doi:10.1109/IEEESTD.2019.8686430. ISBN 978-1-5044-5258-8.

External links[edit]

• IEEE 1801-2018 - free download of the standard.