| Developer(s) | The VTR Development Team |
|---|---|
| Stable release | 8.0.0 / 24 March 2020; 4 years ago (2020-03-24) |
| Repository | |
| Written in | C/C++ |
| Operating system | Unix-like |
| Type | Electronic Design Automation |
| License | MIT License |
| Website | verilogtorouting |
Verilog-to-Routing (VTR) is an open source CAD flow for FPGA devices.[1][2][3] VTR's main purpose is to map a given circuit described in Verilog, a Hardware Description Language, on a given FPGA architecture for research and development purposes; the FPGA architecture targeted could be a novel architecture that a researcher wishes to explore, or it could be an existing commercial FPGA whose architecture has been captured in the VTR input format. The VTR project has many contributors, with lead collaborating universities being the University of Toronto, the University of New Brunswick, and the University of California, Berkeley . Additional contributors include Google, The University of Utah, Princeton University, Altera, Intel, Texas Instruments, and MIT Lincoln Lab.
The VTR design flow usually consists of three main component applications: ODIN II which compiles Verilog code to a circuit in Berkeley Logic Interchange Format (BLIF), a human-readable graph representation of the circuit;[4] ABC which optimizes the BLIF circuit produced by ODIN II; and VPR which packs, places and routes the optimized circuit on the given FPGA architecture. There are some additional optional tools that can process the VTR output further. For example, the FASM FPGA Assembly tool can produce programming bitstreams for some commercial FPGAs (Xilinx Artix and Lattice ice40) at the end of the VTR flow, while the OpenFPGA tool integrates with VTR to produce a standard cell layout of a novel (proposed) FPGA. It is also possible to use different tools for the first (HDL synthesis) stage of the VTR flow; for example the Titan Flow [5] uses Quartus to perform the HDL to logic synthesis stage, and then VPR to perform placement and routing, while Symbiflow uses the Yosys synthesis tool followed by VPR placement and routing.
ODIN II is the HDL compiler of the VTR flow. It transforms a given Verilog code to a BLIF circuit, performs code and circuit optimizations, visualizes circuits,[6] and performs partial mapping of logic to available hard blocks of the given architecture. Also, it can simulate the execution of circuits both for validation as well as power, performance and heat analysis. ODIN II is maintained by the University of New Brunswick.[7]
From the Verilog to Routing website, it is noted: "Odin-II has been deprecated and will be removed in a future version. Now VTR uses Parmys as the default frontend which utilizes Yosys as elaborator with partial mapping features enabled." https://docs.verilogtorouting.org/en/latest/odin/
ABC optimizes BLIF circuits by performing logic optimization and technology mapping. ABC is maintained by the University of California, Berkeley.[8]
Versatile Place and Route (VPR) is the final component of VTR. Its input is a BLIF circuit, which it packs, places and routes on an input FPGA architecture.
During packing, neighboring and related logic elements of the circuit are clustered together into Logic Blocks matching the hardware of the FPGA. During placement, these logic blocks as well as hard blocks are assigned to the available hardware resources of the FPGA. Finally, during routing the signal connections between blocks are made. VPR is primarily developed by the University of Toronto, with contributions from many other universities and companies.[9]
The FPGA Assembly (genfasm) tool will produce a programming bitstream from a VTR implementation (placement and routing of a circuit) on commercial architectures for which complete VTR architecture files describing the FPGA device have been produced. Currently this includes the Xilinx Artix and Lattice ice40 FPGA families. This tool is primarily developed by Google.
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