Contents

Goldmont

Goldmont is a microarchitecture for low-power Atom, Celeron and Pentium branded processors used in systems on a chip (SoCs) made by Intel. They allow only one thread per core.

The Apollo Lake platform with 14 nm Goldmont core was unveiled at the Intel Developer Forum (IDF) in Shenzhen, China, April 2016.^[1] The Goldmont architecture borrows heavily from the Skylake Core processors, so it offers a more than 30 percent performance boost compared to the previous Braswell platform, and it can be used to implement power-efficient low-end devices including Cloudbooks, 2-in-1 netbooks, small PCs, IP cameras, and in-car entertainment systems.^[2][3]

Goldmont is the 2nd generation out-of-order low-power Atom microarchitecture designed for the entry level desktop and notebook computers.^[4] Goldmont is built on the 14 nm manufacturing process and supports up to four cores for the consumer devices. It includes the Intel Gen9 graphics architecture introduced with the Skylake.

The Goldmont microarchitecture builds on the success of the Silvermont microarchitecture, and provides the following enhancements:

• An out-of-order execution engine with a 3-wide superscalar pipeline.^[5] Specifically:
  • The decoder can decode 3 instructions per cycle.
  • The microcode sequencer can send 3 μops per cycle for allocation into the reservation stations.
  • Retirement supports a peak rate of 3 per cycle.
• Enhancement in branch prediction which de-couples the fetch pipeline from the instruction decoder.
• Larger out-of-order execution window and buffers that enable deeper out-of-order execution across integer, FP/SIMD, and memory instruction types.
• Fully out-of-order memory execution and disambiguation. The Goldmont microarchitecture can execute one load and one store per cycle (compared to one load or one store per cycle in the Silvermont microarchitecture). The memory execution pipeline also includes a second level TLB enhancement with 512 entries for 4KB pages.
• Integer execution cluster in the Goldmont microarchitecture provides three pipelines and can execute up to three simple integer ALU operations per cycle.
• SIMD integer and floating-point instructions execute in a 128-bit wide engine. Throughput and latency of many instructions have improved, including PSHUFB with 1-cycle throughput (versus 5 cycles for Silvermont microarchitecture) and many other SIMD instructions with doubled throughput.
• Throughput and latency of instructions for accelerating encryption/decryption (AES) and carry-less multiplication (PCLMULQDQ) have been improved significantly in the Goldmont microarchitecture.
• The Goldmont microarchitecture provides new instructions with hardware accelerated secure hashing algorithm, SHA1 and SHA256.
• The Goldmont microarchitecture also adds support for the RDSEED instruction for random number generation meeting the NIST SP800-90C standard.
• PAUSE instruction latency is optimized to enable better power efficiency.

• A14 nm manufacturing process
• System on chip architecture
• 3D tri-gate transistors
• Consumer chips up to quad-cores
• Supports SSE4.2 instruction set
• Supports Intel AESNI and PCLMUL instructions
• Supports Intel RDRAND and RDSEED instructions
• Supports Intel SHA extensions
• Supports Intel MPX (Memory Protection Extensions)
• Gen 9 Intel HD Graphics with DirectX 12, OpenGL 4.6 with latest Windows 10 driver update^[6] (OpenGL 4.5 on Linux^[7]), OpenGL ES 3.2 and OpenCL 2.0 support.
• HEVC Main10 & VP9 Profile0 hardware decoding support
• 10 Wthermal design power (TDP) Desktop or Server processors
• 4.0 to 6.0 W TDP mobile processors
• eMMC 5.0 technology to connect to NAND flash storage
• USB 3.1 & USB-C specification
• Support for DDR3L, LPDDR3, and LPDDR4 memory
• Integrated Sensor Hub (ISH) which can sample and combine data from individual sensors and operate independently when the host platform is in a low power state
• Image Signal Processor (ISP) supporting four concurrent camera streams
• Audio controller supporting HD Audio and LPE Audio
• Trusted Execution Engine 3.0 security subsystem

Similar to the previous Silvermont generation, design flaws were found in processor circuitry, resulting in cease of operation when processors are actively used for several years. An Erratum named APL46 "System May Experience Inability to Boot or May Cease Operation"^[8] was added to documentation in June 2017, stating that low pin count (LPC), real time clock (RTC), SD card and GPIO interfaces may stop functioning.

Mitigations^[9] were found to limit impact on systems. A firmware update for the LPC bus called LPC_CLKRUN# reduces the utilization of the LPC interface, which in turn decreases (but does not eliminate) LPC bus degradation – some systems are however not compatible with this new firmware. It is recommended not to use SD cards as boot devices, and to remove the card from the system when not in use; other possible solutions being using only UHS-I cards and operating them at 1.8 V.

Congatec also states the issues impacts USB buses and eMMC, although those are not mentioned in Intel's public documentation. USB should have a maximum of 12% active time and there is a 60TB transmit traffic life expectancy over the lifetime of the port. eMMC should have a maximum of 33% active time and should be set to D3 device low power state by the operating system when not in use. Newer designs such as Atom C3000 Denverton do not seem to be affected.^[10]

List of desktop processors as follows:^[3][11]

List of mobile processors as follows:^[3][11]

List of embedded processors as follows:

There is also an Atom A3900 series exclusively for automotive customers with AEC-Q100 qualification:^[14]

Willow Trail platform was canceled. Apollo Lake will be offered instead.^[15]

• List of Intel CPU microarchitectures
• List of Intel Pentium microprocessors
• List of Intel Celeron microprocessors
• List of Intel Atom microprocessors
• Atom (system on chip)