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Gracemont (microarchitecture)

Gracemont

General information
Launched	November 4, 2021; 2 years ago (2021-11-04)[1]
Marketed by	Intel
Designed by	Intel
Common manufacturer	Intel
Performance
Max. CPU clock rate	0.7 GHz to 4.3 GHz
Cache
L1 cache	96 KB per core: 64 KB instructions 32 KB data
L2 cache	2 or 4 MB per module
L3 cache	3 MB per module
Architecture and classification
Instruction set	x86-64
Extensions	MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, AVX, AVX2, FMA3, AVX-VNNI, AES-NI, CLMUL, RDRAND, SHA, TXT, VT-d, VT-x
Physical specifications
Cores	4 per module
Products, models, variants
Product code names	Alder Lake (client) Raptor Lake (client)
History
Predecessor	Tremont
Successor	Crestmont

Gracemont is a microarchitecture for low-power processors used in systems on a chip (SoCs) made by Intel, and is the successor to Tremont. Like its predecessor, it is also implemented as low-power cores in a hybrid design of the Alder Lake, Raptor Lake and Raptor Lake Refresh processors.^[2]

Design[edit]

Gracemont is the fourth generation out-of-order low-power Atom microarchitecture, built on the Intel 7 manufacturing process.^[3]

The Gracemont microarchitecture has the following enhancements over Tremont:^[4][3]

• Level 1 cache per core:
  • eight-way-associative 64 KB instruction cache
  • eight-way-associative 32 KB data cache
• New On-Demand Instruction Length Decoder
• Instruction issue increased to five per clock (from four)
• Instruction retire increased to eight per clock (from seven)
• Execution ports (functional units) there are now 17 (from eight)
• Reorder buffer increased to 256 entries (from 208)
• Improved branch prediction
• Support for AVX, AVX2, FMA3 and AVX-VNNI instructions^[5]
• 2 or 4 MB shared L2 cache per 4-core cluster^[3] Alder Lake-S/H/P/U family has 2 MB. Raptor Lake-S/H/P/U family has 4 MB.

Technology[edit]

• System on a chip (SoC) architecture
• 3D tri-gate transistors
• Thermal design power (TDP)
  • 10 W desktop processors
  • 6 W mobile processors

List of Gracemont processors[edit]

The microarchitecture is used as the efficient cores of the 12th generation of Intel Core hybrid processors (codenamed "Alder Lake"), the 13th generation of Intel Core hybrid processors (codenamed "Raptor Lake") and the 14th generation of Intel Core hybrid processors (codenamed "Raptor Lake Refresh"). It's used exclusively in the Alder Lake-N line-up.

Alder Lake-N[edit]

See also[edit]

• List of Intel CPU microarchitectures

References[edit]

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